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Ethernet TSN Bridge

A complete integrated hardware and software subsystem that combines a TSN capable Ethernet switch, DMA engine and IEEE 802.1AS time synchronisation.

Overview

A bridge connects multiple TSN enabled network segments while ensuring deterministic,low-latency communication.

Like a traditional Ethernet switch it forwards frames between ports based on MAC addresses, but it also adds TSN scheduling, filtering, and traffic management for reliable, time-critical communication. Comcores offers a versatile Bridge subsystem IP tailored to a range of performance levels and TSN feature sets which is suited for demanding applications in automotive, industrial, avionics, and defence.

The Bridge subsystem IP integrates hardware and software in one subsystem, connecting to embedded processors through an AXI Memory-Mapped interface for frame exchange and an AXI4-Lite interface for management and configuration.

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Evaluate in Hardware

Omni500 Platform
Configurable evaluation and prototyping platform for deterministic Ethernet.

Key Capabilities

TSN Capable Ethernet Switch Core
–Automotive, Aerospace & Industrial Automation TSN Profiles
Functional Safety Ready
–ISO 26262 / ASIL aligned, 10BASE-T1S
Cut-through operation
–Low latency frame processing / forwarding
Integrated multichannel DMA engine
–Single & Multicore embedded processor systems
Customizable solution
–Bespoke configuration to match individual project requirements
Software Stack
–Multiple operating systems

Target Markets

Automotive

Zonal and software-defined-vehicle networks needing deterministic in-vehicle Ethernet.

Industrial

Factory automation, robotics, and motion control based on Ethernet networks.

Avionics

Redundant, time-synchronised networks for safety-critical aircraft systems.

Defence

Secure, deterministic communication with link-layer encryption.

Block Diagram

SVG Grey Bridge

Ethernet TSN Bridge 

Simplified architecture, the full diagram with all interfaces and options available in the datasheet.

Technical Specifications

Ports & PHY interface

Physical ports
Up to 32 at 10M / 100M / 1G / 2.5G, plus 2 at 10 Gbps
PHY interfaces
MII, RMII, GMII, RGMII, SGMII, USGMII, USXGMII, XFI
Single Pair Ethernet
10GBASE-T1S DigiPHY OA3P Interface
PHY management
Built-in MDIO controller

TSN & traffic management

Traffic shaping
Time-Aware Shaping (TAS), Credit-Based Shaping (CBS), Asynchronous Traffic Shaping (ATS)
Frame preemption
Preemptive MAC — high-priority frames interrupt lower-priority traffic
Reliability
Frame Replication & Elimination — IEEE 802.1CB (FRER)
Stream policing
Per-stream filtering & policing — IEEE 802.1Qci
VLAN & QoS
IEEE 802.1Q — up to 8 traffic classes
Forwarding
Cut-through & store-and-forward

Timing & synchronisation

Time sync
IEEE 802.1AS and amendment IEEE 802.1ASds (half-duplex)
Clocking
Built-in wall clock and phase adjustment — reduces CPU sync load

System Integration

Frame interface
AXI Memory-Mapped
Management interface
AXI4-Lite, APB
DMA Integrated engine
Minimal CPU interaction for frame transfer
Technology
Silicon Agnostic for both ASIC or FPGA

Software

Operating System
FreeRTOS / Ziphyr / Linux
Timing
IEEE 802.1AS software stack

Security

MACsec (optional)
IEEE 802.1AE — port authentication, encryption, integrity; multiple SecYs per port

Technical Support & Deliverables

Technical Support

Access to JIRA support system and direct engineer support are part of our support package to help customers during their developement and integration phases.

Deliverables

Comcores IP includes everything needed to integrate, verify and deploy including:


Bespoke RTL as source code or encrypted code

Solid documentation, including User Manual and Release Note

Simulation Environment, including Testbed, Test cases and Test Script

Programming Register Specification

Timing Constraints in Synopsys SDC format

Synopsys SGDC Files (optional)

Synopsys Lint, CDC and Waivers (optional)

Omni500 – Configurable evaluation and prototyping platform

The Omni500 is a configurable evaluation and prototyping platform for deterministic Ethernet systems from 10 Mb/s to 1 Gb/s. It combines TSN networking, multi-speed Ethernet interfaces, and field buses into one compact platform for validation, development, and system integration.

Omni500 is built on combining an AMD Artix UltraScale+ FPGA, Linux-capable control processor, and a comprehensive set of interfaces.

Built for engineers who need deterministic results. The platform handles all real-time packet processing and timestamping in hardware, while the Linux control layer provides the flexibility of a full software stack — Web GUI, REST API, and SDK included.

Omni500 Product image

Related Products

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Ultra Compact solution that can interface with nearly any microcontroller or embedded processor system.

Zonal Controller

Automotive TSN IP with Ethernet switching, Root of Trust, and IEEE 1722 support.

Blogs & Whitepapers

What is TSN?

What is TSN?

TSN, or Time-Sensitive Networking, is a technology based on the IEEE 802.1Q standard. It has evolved from the Ethernet technology currently used to carry all types of traffic, for which ethernet was not originally intended, such as multiple data flows with different...

read more