Chip to Chip
Cutting Edge Chip to Chip Solutions
Overview
Comcores chip-to-chip portfolio consists of JESD204B, JESD204C, JESD204 Verification IP and Interlaken IP. Comcores is a leading provider of JESD204B and JESD204C. The JESD IP comes with the widest parameter set available and has gone through extensive testing. The JESD IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option.
The JESD204B and JESD204C IP Cores are silicon proven, thoroughly tested in UVM regression environment and have been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions. The Interlaken IP supports up to 2.6 Tbps bandwidth performance on up to 48 lanes with 56 Gbps Serdes rates and comes with an integrated Media Access layer.
Architecture Diagram
Success Story
Customer experience
Customer: Key OEM | Location: South Korea
Challenge
Building a 5G chip for processing massive MIMO requiring exchange of a massive amount of data
Solution
Comcores’ unique interface technology enabled our customer to build a state-of-the-art chip with terabytes of interface capability and with a lot of flexibility to host different configurations.
Comcores unique insight and experience with these interface protocols provided the customer with a partner that could actively provide advice for design decisions and ensure a safe way to final success.
Related material
Comcores Webinar: “Bridging Analog and Digital worlds at high speed with the JESD204 serial interface”
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
Piotr Koziuk Jan 13 2022 To meet the increased demand for converter speed and resolution, JEDEC proposed the JESD204 standard describing a new efficient serial interface to handle data converters. In 2006, the JESD204 standard offered support for multiple data converters over a single lane with the following standard revisions; A, B, and C successively adding features such as support for multiple lanes, deterministic latency, and error detection and correction while constantly increasing Lane...
Interlaken IP Core for high-speed chip-to-chip applications is now available
Press Release Copenhagen, Denmark, September 29, 2021 - Comcores ApS, a fast-growing specialized supplier of Intellectual Property (IP) Cores expands its Chip-to-chip Interface IP portfolio by announcing the availability of a high-performance Interlaken IP. Comcores as the leading provider of silicon-proven JESD204B and JESD204C Controller IPs, now introduces a high-performance Interlaken IP, a silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting any ASIC or...