1. Home
  2. Chip to Chip Solutions

Chip to Chip

Cutting Edge Chip to Chip Solutions

3

Overview

Comcores chip-to-chip portfolio consists of JESD204B, JESD204C, JESD204 Verification IP and Interlaken IP. Comcores is a leading provider of JESD204B and JESD204C. The JESD IP comes with the widest parameter set available and has gone through extensive testing. The JESD IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option.

 

The JESD204B and JESD204C IP Cores are silicon proven, thoroughly tested in UVM regression environment and have been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions. The Interlaken IP supports up to 2.6 Tbps bandwidth performance on up to 48 lanes with 56 Gbps Serdes rates and comes with an integrated Media Access layer.

Architecture Diagram

JESD204 diagram

Success Story

Customer experience

Customer: Key OEM  |  Location: South Korea

Challenge

Building a 5G chip for processing massive MIMO requiring exchange of a massive amount of data

$

Solution

Comcores’ unique interface technology enabled our customer to build a state-of-the-art chip with terabytes of interface capability and with a lot of flexibility to host different configurations.

Comcores unique insight and experience with these interface protocols provided the customer with a partner that could actively provide advice for design decisions and ensure a safe way to final success.

Related material

Unlock your chips full data transfer potential with Interlaken

WHITEPAPER System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume less power-per-bit at a lower cost-per-bit. Reliability is, of course, a key requirement, but not at the expense of efficiency and cost. Interlaken provides a high-speed interface with efficiency, reliability and scalability. The design of the Interlaken interface ensures low power consumption and...

read more

Unlock your chips full data throughput potential with Interlaken

Piotr Koziuk Sep 12 2022 Way back in the early 2000's when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features, lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s flow control capabilities. To this day the continuous growth in data consumption is driving demand for higher speeds, but also lower...

read more