Chip to Chip
Cutting Edge Chip to Chip Solutions
Overview
Comcores chip-to-chip portfolio consists of JESD204B, JESD204C, JESD204D and JESD204 Verification IP and Interlaken IP. Comcores is a leading provider of JESD204B and JESD204C. The JESD IP comes with the widest parameter set available and has gone through extensive testing. The JESD IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option.
The JESD204B and JESD204C IP Cores are silicon proven, thoroughly tested in UVM regression environment and have been interoperability tested with key ADC/DAC providers and leading Serdes PHY solutions. The Interlaken IP supports up to 2.6 Tbps bandwidth performance on up to 48 lanes with 56 Gbps Serdes rates and comes with an integrated Media Access layer.
Architecture Diagram
Success Story
Customer experience
Customer: Key OEM | Location: South Korea
Challenge
Building a 5G chip for processing massive MIMO requiring exchange of a massive amount of data
Solution
Comcores’ unique interface technology enabled our customer to build a state-of-the-art chip with terabytes of interface capability and with a lot of flexibility to host different configurations.
Comcores unique insight and experience with these interface protocols provided the customer with a partner that could actively provide advice for design decisions and ensure a safe way to final success.
Related material
JESD204D Webinar: Expert insights into what we Expect and how to Prepare for the upcoming Standard
Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based our experience working with JESD204. Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward...
What is interlaken?
Morten Kofoed Esbjørn - Oct 31, 2022. Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the...
Unlock your chips full data transfer potential with Interlaken
WHITEPAPER - Unlock your chips full data transfer potential with Interlaken As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. Interlaken addresses modern chip-to-chip design challenges System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume...