Interlaken
Overview
Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated Media Access layer.
Learn more by reading our blog post, read our whitepaper or watch our webinar on the Interlaken IP.
Key Features
Richly Featured
- MAC layer with fast AMBA CXS interface
- PCS layer highly configurable with up to 48 lanes
- Multi-lane configurations, up to 48 lanes
- 64B 67B encoding/decoding supported
- Supports up to 2048 logic channels
- Programmable Meta Frame lengths
- Programmable Interlaken Bursts: Short from 32 and Max up to 1024 Bytes
- Flow control support
- Mode of operation: Packet mode and Interleave mode supported
- Re-transmit
- Interlaken Dual Calendar
- Look-Aside
- FEC support
Easy to use
- Solid documentation including integration guide
- Easy to use RTL test environment
- No special software required
- Strong engineering support for bring-up
Solid
- SystemVerilog random regression tested
- Lint/CDC checked
Silicon Agnostic
- Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Interlaken Content
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Comcores Unveils JESD204 IP Core Integration Guide to Streamline Customer PHY Integration Challenges
Press Release Copenhagen, Denmark, June 27, 2023 - Through our global leadership within JESD204 IP, Comcores has recognized the challenges faced by customers when integrating the PHY (Physical Layer) with JESD204 IP cores. Having partnered with over 50 customers on various JESD204 projects, Comcores understands the complexity and associated pains involved in this process. Comcores wants to share our learnings for the benefit of our customers. Therefore, Comcores introduces a new initiative...
JESD204D Webinar: Expert insights into what we Expect and how to Prepare for the upcoming Standard
Leading Aerospace and Defense Company purchases Interlaken IP core from Comcores
Press Release Copenhagen, Denmark, June 7, 2023 - A leading company in the defense and aerospace industry, has purchased the Interlaken IP core from Comcores to meet its high-speed data transfer requirements. This strategic investment aims to enhance data transfer capabilities in both their Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA) implementations utilizing speeds of 256 Gbps. Interlaken, a lightweight and feature-rich data transfer protocol, will...