Interlaken
Overview
The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6Tbps high-bandwidth performance and comes with an integrated Media Access layer.
The IP can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in both number of lanes and lane speed. The IP core is heavily tested in SystemVerilog random regression environment.
Block Diagram
Key Features
Richly Featured
- MAC layer with fast AMBA CXS interface
- PCS layer highly configurable
- 64b67b encoding/decoding supported
Solid
- SystemVerilog random regression tested
- Lint/CDC checked
Easy to use
- Solid documentation including integration guide
- Easy to use RTL test environment
- No special software required
- Strong engineering support for bring-up
Silicon Agnostic
- Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Unlock your chips full data transfer potential with Interlaken
WHITEPAPER System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume less power-per-bit at a lower cost-per-bit. Reliability is, of course, a key requirement, but not at the expense of efficiency and cost. Interlaken provides a high-speed interface with efficiency, reliability and scalability. The design of the Interlaken interface ensures low power consumption and...
Unlock your chips full data throughput potential with Interlaken
Piotr Koziuk Sep 12 2022 Way back in the early 2000's when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features, lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s flow control capabilities. To this day the continuous growth in data consumption is driving demand for higher speeds, but also lower...
CEO Interview
Daniel Nenni of SemiWiki interviewed John Mortensen, the CEO of Comcores. Feb 18 2022 Bio of John Mortensen John is the CEO & CCO of Comcores. He has been with Comcores since 2019, and has been leading the commercial function since 2020 and was appointed CEO in early 2021. John is focused on creating the best possible customer experience when you do business with Comcores. An experience where you, as a customer, sense how we constantly strive to develop cutting-edge IP’s, how we make an...