Overview

Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated Media Access layer.

The Interlaken Controller can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in number of logic channels (up to 2048), lanes (up to 48) and lane speed (up to 56 Gbps). The IP core is heavily tested in SystemVerilog random regression environment.

Learn more by reading our blog post, read our whitepaper or watch our webinar on the Interlaken IP.

Block Diagram

Comcores Interlaken diagram

Key Features

Richly Featured

  • MAC layer with fast AMBA CXS interface
  • PCS layer highly configurable with up to 48 lanes
  • Multi-lane configurations, up to 48 lanes
  • 64B 67B encoding/decoding supported
  • Supports up to 2048 logic channels
  • Programmable Meta Frame lengths
  • Programmable Interlaken Bursts: Short from 32 and Max up to 1024 Bytes
  • Flow control support
  • Mode of operation: Packet mode and Interleave mode supported
  • Re-transmit
  • Interlaken Dual Calendar
  • Look-Aside
  • FEC support

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up

Solid

  • SystemVerilog random regression tested
  • Lint/CDC checked

Silicon Agnostic

  • Targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Programming Register Specification.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers.
  • Test Report (optional)
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Interlaken Content

Related Products

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

Comcores JESD204D IP core conforming to the Revision D of the JESD204 standard released in Dec’2023 now available

Press Release Copenhagen, Denmark, Jan 8, 2024 - At Comcores we want to keep enabling our customers with the latest IPs and to meet this requirement, for a major part of the last year we have been working on developing our JESD204D IP which was designed based on our understanding of the how the needs of the serialized interface between data converters and logic devices will evolve and a premption of what the JEDEC standards committee would consider as part of the upcoming D revision to the...

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Comcores Unveils JESD204 IP Core Integration Guide to Streamline Customer PHY Integration Challenges

Press Release Copenhagen, Denmark, June 27, 2023 - Through our global leadership within JESD204 IP, Comcores has recognized the challenges faced by customers when integrating the PHY (Physical Layer) with JESD204 IP cores. Having partnered with over 50 customers on various JESD204 projects, Comcores understands the complexity and associated pains involved in this process. Comcores wants to share our learnings for the benefit of our customers. Therefore, Comcores introduces a new initiative...

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