Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated Media Access layer.

The Interlaken Controller can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in number of logic channels (up to 2048), lanes (up to 48) and lane speed (up to 56 Gbps). The IP core is heavily tested in SystemVerilog random regression environment.

Learn more by reading our blog post, read our whitepaper or watch our webinar on the Interlaken IP.

Block Diagram

Comcores Interlaken diagram

Key Features

Richly Featured

  • MAC layer with fast AMBA CXS interface
  • PCS layer highly configurable with up to 48 lanes
  • Multi-lane configurations, up to 48 lanes
  • 64B 67B encoding/decoding supported
  • Supports up to 2048 logic channels
  • Programmable Meta Frame lengths
  • Programmable Interlaken Bursts: Short from 32 and Max up to 1024 Bytes
  • Flow control support
  • Mode of operation: Packet mode and Interleave mode supported
  • Re-transmit
  • Interlaken Dual Calendar
  • Look-Aside
  • FEC support

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up


  • SystemVerilog random regression tested
  • Lint/CDC checked

Silicon Agnostic

  • Targeting both ASICs and FPGAs


The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Programming Register Specification.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers.
  • Test Report (optional)
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Interlaken Content

Related Products

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research


Long-term experience in communication protocols

Expert in executing digital design projects

Unlock your chips full data transfer potential with Interlaken

WHITEPAPER - Unlock your chips full data transfer potential with Interlaken As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. Interlaken addresses modern chip-to-chip design challenges System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume...

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Unlock your chips full data throughput potential with Interlaken

Piotr Koziuk - Sep 12, 2022. Way back in the early 2000's when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features, lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s flow control capabilities. To this day the continuous growth in data consumption is driving demand for higher speeds, but also lower...

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