JESD204 Verification IP
Overview
With a solid track record in delivering JESD 204B and C solutions, Comcores offers a best-in-class verification IP for JESD204 that supports verification of both B- and C-versions of the standard. The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
The JESD204 VIP provides easy integration and configuration abilities and is delivered with a set of test cases.
Comcores JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support.
Learn more about the JESD204 standard.
Block Diagram
Key Features
High Performance
- Fully compatible with JESD204B and JESD204C specifications
- System Verilog and UVM methodology support
- All types of subclasses: 0, 1, 2
- Supports Transmitter and Receiver Mode
Richly Featured
- Scrambling
- Forward Error Correction (FEC)
- 8b10b, 64b66b and 64b80b PCS
- Extensive error injection
- Built-in protocol checks
Easy to use
- Runs on all main simulators with UVM support
- Verification plan and coverage
- Solid documentation and strong support
Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script and Random Tests.
- Error Scenario Tests and Basic and Directed Protocol tests (optional).
- Access to support system and direct support from Comcores Engineers.
Please contact us to discuss your project requirements.
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Unlock your chips full data transfer potential with Interlaken
WHITEPAPER System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume less power-per-bit at a lower cost-per-bit. Reliability is, of course, a key requirement, but not at the expense of efficiency and cost. Interlaken provides a high-speed interface with efficiency, reliability and scalability. The design of the Interlaken interface ensures low power consumption and...
Unlock your chips full data throughput potential with Interlaken
Piotr Koziuk Sep 12 2022 Way back in the early 2000's when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features, lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s flow control capabilities. To this day the continuous growth in data consumption is driving demand for higher speeds, but also lower...
CEO Interview
Daniel Nenni of SemiWiki interviewed John Mortensen, the CEO of Comcores. Feb 18 2022 Bio of John Mortensen John is the CEO & CCO of Comcores. He has been with Comcores since 2019, and has been leading the commercial function since 2020 and was appointed CEO in early 2021. John is focused on creating the best possible customer experience when you do business with Comcores. An experience where you, as a customer, sense how we constantly strive to develop cutting-edge IP’s, how we make an...