JESD204 Verification IP

Overview

Comcores has a solid track record of delivering JESD204B and JESD204C solutions, to support the IPs we offer the verification IP for JESD204, which supports both the JESD204B and JESD204C version. Furthermore, it will support JESD204D (once the standard is published). The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.

The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product. Comcores JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support.

Learn more about the JESD204 (the history, use cases and common pit falls) by viewing our webinar.

Block Diagram

Block Diagram of Comcores JESD204B IP

Key Features

Richly Featured

  • Supports 32bit data width per converter
  • Supports multiple samples per converter per frame cycle
  • Supports up to 24 lanes
  • Supports 8b 10b link layer functions.
  • Supports 64b 66b link layer functions
  • Scrambling
  • Forward Error Correction (FEC) – For JESD204C
  • Reed-Solomon FEC (RS-FEC) – For JESD204D
  • RS-FEC encoding, 64b 66b, 64b 80b and 8b 10b
  • Extensive error injection and detection
  • Built-in protocol checks
  • Supports Lane alignment monitoring, correction and character replacement

High Performance

  • Fully compatible with JESD204B and JESD204C specifications, and Comcores RS-FEC early adopters implementation for JESD204D
  • SystemVerilog and UVM methodology support
  • All types of subclasses: 0, 1, 2
  • Supports Transmitter and Receiver Mode

​Easy to use

  • Runs on all main simulators with UVM support
  • Verification plan and coverage
  • Solid documentation and strong support

Interoperability

  • JESD204B IP has been interoperability tested with a variety of data converters
  • JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case, Test Script and Random Tests.
  • Error Scenario Tests and Basic and Directed Protocol tests (optional).
  • Access to support system and direct support from Comcores Engineers.

Related Products

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

Comcores JESD204D IP core conforming to the Revision D of the JESD204 standard released in Dec’2023 now available

Press Release Copenhagen, Denmark, Jan 8, 2024 - At Comcores we want to keep enabling our customers with the latest IPs and to meet this requirement, for a major part of the last year we have been working on developing our JESD204D IP which was designed based on our understanding of the how the needs of the serialized interface between data converters and logic devices will evolve and a premption of what the JEDEC standards committee would consider as part of the upcoming D revision to the...

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Comcores Unveils JESD204 IP Core Integration Guide to Streamline Customer PHY Integration Challenges

Press Release Copenhagen, Denmark, June 27, 2023 - Through our global leadership within JESD204 IP, Comcores has recognized the challenges faced by customers when integrating the PHY (Physical Layer) with JESD204 IP cores. Having partnered with over 50 customers on various JESD204 projects, Comcores understands the complexity and associated pains involved in this process. Comcores wants to share our learnings for the benefit of our customers. Therefore, Comcores introduces a new initiative...

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