JESD204 Verification IP
Overview
With a solid track record in delivering JESD 204B and C solutions, Comcores offers a best-in-class verification IP for JESD204 that supports verification of both B- and C-versions of the standard. The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
The JESD204 VIP provides easy integration and configuration abilities and is delivered with a set of test cases.
Comcores JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support.
Block Diagram
Key Features
High Performance
- Fully compatible with JESD204B and JESD204C specifications
- System Verilog and UVM methodology support
- All types of subclasses: 0, 1, 2
- Supports Transmitter and Receiver Mode
Richly Featured
- Scrambling
- Forward Error Correction (FEC)
- 8b10b, 64b66b and 64b80b PCS
- Extensive error injection
- Built-in protocol checks
Easy to use
- Runs on all main simulators with UVM support
- Verification plan and coverage
- Solid documentation and strong support
Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions
Deliverables
The IP core comes deeply verified, interoperability tested and with extensive documentation that, among others, includes User Manual and Release note. The product comes with a Basic RTL Test Bench, Constraint Files, Test Cases and Test Reports. UVM VIP and HW validation Platform available for purchase.
The core will by default come in an encrypted format. Source code option is available.
Please Contact us to discuss your project requirements.
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
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