JESD204 Verification IP
Comcores has a solid track record of delivering JESD204B and JESD204C solutions, to support the IPs we offer the verification IP for JESD204, which supports both the JESD204B and JESD204C version. Furthermore, it will support JESD204D (once the standard is published). The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product. Comcores JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support.
Learn more about the JESD204 standard.
- Supports 32bit data width per converter
- Supports multiple samples per converter per frame cycle
- Supports up to 24 lanes
- Supports 8b/10b link layer functions.
- Supports 64b/66b link layer functions
- Forward Error Correction (FEC) – For JESD204C
- Reed-Solomon FEC (RS-FEC) – For JESD204D
- RS-FEC encoding, 64b66b, 64b80b and 8b10b
- Extensive error injection and detection
- Built-in protocol checks
- Supports Lane alignment monitoring, correction and character replacement
- Fully compatible with JESD204B and JESD204C specifications, and Comcores RS-FEC early adopters implementation for JESD204D
- SystemVerilog and UVM methodology support
- All types of subclasses: 0, 1, 2
- Supports Transmitter and Receiver Mode
Easy to use
- Runs on all main simulators with UVM support
- Verification plan and coverage
- Solid documentation and strong support
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script and Random Tests.
- Error Scenario Tests and Basic and Directed Protocol tests (optional).
- Access to support system and direct support from Comcores Engineers.
What Comcores IP will do for you
Solid process and predictability
First in bringing out new solutions
Tremendous investments in research
Long-term experience in communication protocols
Expert in executing digital design projects
Predictions and expectations of the upcoming JESD204D standard
Morten Kofoed Esbjørn - May 2, 2023.JESD204 Standard which was first introduced in 2006 is one of the key standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) and has come a long way since its introduction, evolving with multiple iterations from JESD204B to JESD204C. The latest iteration of this standard the JESD204D is expected to release in Q4 2023 and if you are curious about the latest developments expected in the JESD204 standard, then...
JESD204D Webinar: Expert insights into what we Expect and how to Prepare for the upcoming Standard
Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based our experience working with JESD204. Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward...
What is interlaken?
Morten Kofoed Esbjørn - Oct 31, 2022. Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the...