JESD204 Verification IP

Overview

Comcores has a solid track record of delivering JESD204B and JESD204C solutions, to support the IPs we offer the verification IP for JESD204, which supports both the JESD204B and JESD204C version. Furthermore, it will support JESD204D (once the standard is published). The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.

The verification IP helps reduce time to test, accelerate verification process and ensures a high quality for the end-product. Comcores JESD204 VIP is prepared for seamless functionality on all major simulators with UVM support.

Learn more about the JESD204 (the history, use cases and common pit falls) by viewing our webinar.

Block Diagram

Block Diagram of Comcores JESD204B IP

Key Features

Richly Featured

  • Supports 32bit data width per converter
  • Supports multiple samples per converter per frame cycle
  • Supports up to 24 lanes
  • Supports 8b 10b link layer functions.
  • Supports 64b 66b link layer functions
  • Scrambling
  • Forward Error Correction (FEC) – For JESD204C
  • Reed-Solomon FEC (RS-FEC) – For JESD204D
  • RS-FEC encoding, 64b 66b, 64b 80b and 8b 10b
  • Extensive error injection and detection
  • Built-in protocol checks
  • Supports Lane alignment monitoring, correction and character replacement

High Performance

  • Fully compatible with JESD204B and JESD204C specifications, and Comcores RS-FEC early adopters implementation for JESD204D
  • SystemVerilog and UVM methodology support
  • All types of subclasses: 0, 1, 2
  • Supports Transmitter and Receiver Mode

​Easy to use

  • Runs on all main simulators with UVM support
  • Verification plan and coverage
  • Solid documentation and strong support

Interoperability

  • JESD204B IP has been interoperability tested with a variety of data converters
  • JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case, Test Script and Random Tests.
  • Error Scenario Tests and Basic and Directed Protocol tests (optional).
  • Access to support system and direct support from Comcores Engineers.

Related Products

What Comcores IP will do for you

R

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

Leading Aerospace and Defense Company purchases Interlaken IP core from Comcores

Press Release  Copenhagen, Denmark, June 7, 2023 - A leading company in the defense and aerospace industry, has purchased the Interlaken IP core from Comcores to meet its high-speed data transfer requirements. This strategic investment aims to enhance data transfer capabilities in both their Application-Specific Integrated Circuit (ASIC) and Field-Programmable Gate Array (FPGA) implementations utilizing speeds of 256 Gbps. Interlaken, a lightweight and feature-rich data transfer protocol,...

read more

Predictions and expectations of the upcoming JESD204D standard

May 2, 2023.The JESD204 Standard which was first introduced in 2006 is one of the key standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) and has come a long way since its introduction, evolving with multiple iterations from JESD204B to JESD204C. The latest iteration of this standard the JESD204D is expected to release in Q4 2023 and if you are curious about the latest developments expected in the JESD204 standard, then keep reading on as we...

read more

JESD204D Webinar: Expert insights into what we Expect and how to Prepare for the upcoming Standard

Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based our experience working with JESD204. Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward...

read more