JESD204 Verification IP
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script and Random Tests.
- Error Scenario Tests and Basic and Directed Protocol tests (optional).
- Access to support system and direct support from Comcores Engineers.
What Comcores IP will do for you
Solid process and predictability
First in bringing out new solutions
Tremendous investments in research
Long-term experience in communication protocols
Expert in executing digital design projects
Morten Kofoed Esbjørn - May 2, 2023.The JESD204 Standard which was first introduced in 2006 is one of the key standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) and has come a long way since its introduction, evolving with multiple iterations from JESD204B to JESD204C. The latest iteration of this standard the JESD204D is expected to release in Q4 2023 and if you are curious about the latest developments expected in the JESD204 standard,...
Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based our experience working with JESD204. Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward...
Morten Kofoed Esbjørn - Oct 31, 2022. Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the...