JESD204 Verification IP
Overview
Comcores has a solid track record of delivering JESD204B and JESD204C solutions, to support the IPs we offer the verification IP for JESD204, which supports both the JESD204B and JESD204C version. Furthermore, it will support JESD204D (once the standard is published). The JESD204 Verification IP provides an advanced and efficient solution for verifying and debugging these standards in a UVM simulation environment.
Learn more about the JESD204 (the history, use cases and common pit falls) by viewing our webinar.
Block Diagram
Key Features
Richly Featured
- Supports 32bit data width per converter
- Supports multiple samples per converter per frame cycle
- Supports up to 24 lanes
- Supports 8b 10b link layer functions.
- Supports 64b 66b link layer functions
- Scrambling
- Forward Error Correction (FEC) – For JESD204C
- Reed-Solomon FEC (RS-FEC) – For JESD204D
- RS-FEC encoding, 64b 66b, 64b 80b and 8b 10b
- Extensive error injection and detection
- Built-in protocol checks
- Supports Lane alignment monitoring, correction and character replacement
High Performance
- Fully compatible with JESD204B and JESD204C specifications, and Comcores RS-FEC early adopters implementation for JESD204D
- SystemVerilog and UVM methodology support
- All types of subclasses: 0, 1, 2
- Supports Transmitter and Receiver Mode
Easy to use
- Runs on all main simulators with UVM support
- Verification plan and coverage
- Solid documentation and strong support
Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script and Random Tests.
- Error Scenario Tests and Basic and Directed Protocol tests (optional).
- Access to support system and direct support from Comcores Engineers.
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
CEO Interview
Daniel Nenni of SemiWiki interviewed John Mortensen, the CEO of Comcores. Feb 18, 2022. Bio of John Mortensen: John is the CEO & CCO of Comcores. He has been with Comcores since 2019, and has been leading the commercial function since 2020 and was appointed CEO in early 2021. John is focused on creating the best possible customer experience when you do business with Comcores. An experience where you, as a customer, sense how we constantly strive to develop cutting-edge IP’s, how we make an...
JESD204 Webinar: “Bridging Analog and Digital worlds at high speed with the JESD204 serial interface”
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
Piotr Koziuk - Jan 13, 2022. To meet the increased demand for converter speed and resolution, JEDEC proposed the JESD204 standard describing a new efficient serial interface to handle data converters. In 2006, the JESD204 standard offered support for multiple data converters over a single lane with the following standard revisions; A, B, and C successively adding features such as support for multiple lanes, deterministic latency, and error detection and correction while constantly increasing...