JESD204B
Overview
The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b10b encoding.
The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
Learn more about the JESD204 standard.
Block Diagram
Key Features
Delivering Performance
- Designed to JEDEC JESD204B specification
- Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 25 Gbps)
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Checks link configuration data with user selected parameter values during initial lane synchronization sequence
- 8b10b encoding
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1, and 2) on the 8b10b link layer
Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of SerDes PHY solutions
Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Applications
High speed data acquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Please contact us to discuss your project requirements.
Items available for purchase
- UVM VIP
- HW Validation Platform
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
What is interlaken?
Morten Kofoed Esbjørn Oct 31 2022, Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the...
Unlock your chips full data transfer potential with Interlaken
WHITEPAPER - Unlock your chips full data transfer potential with Interlaken As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. Interlaken addresses modern chip-to-chip design challenges System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume...
Unlock your chips full data throughput potential with Interlaken
Piotr Koziuk Sep 12 2022, Way back in the early 2000's when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features, lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s flow control capabilities. To this day the continuous growth in data consumption is driving demand for higher speeds, but also lower...