Select Page
wtfdivi014-url19

JESD204B

Overview

The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, FPGA or ASSP technologies. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization.

The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, 

 

that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP-core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key ADC/DAC providers and leading Serdes/PHY solutions.

Block Diagram

JESD204B Block Diagram

Key Features

Delivering Performance

  • Designed to JEDEC JESD204B specification
  • Line rates from 1 Gb/s to 12.5 Gb/s (with optional extention to 25 Gb/s
  • Supports 1-24 lanes
  • Supports 1-8 converters
  • HD-mode supported
  • Performs user-enabled scrambling
  • Generates initial lane alignment sequence
  • Performs the alignment character generation
  • Sources link configuration data with user selected parameter values during initial lane synchronization sequence
  • Performs 8B/10B encoding
  • Verilog-based
  • Optional data mapping and de-mapping
  • Supports Subclasses 0, 1, and 2
  • Internal clock generation

Easy to use

  • HW demonstration platform available
  • VIP and regression test suite available
  • SerDes interoperability with several major vendors
  • Simple test bench is included
  • Designed in Verilog and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Applications

High speed data arcquisition systems

  • Wireless infrastructure transceiver architectures
  • Radar systems
  • Software-defined radios
  • Portable instrumentation
  • Medical ultrasound equipment

Interoperability

  • JESD204B IP has been interoperability tested with a variety of data converters
  • JESD204B IP has been interoperability tested with key providers of PHY/Serdes solutions

Deliverables

The IP core comes deeply verified, interoperability tested with majority of PHY/Serdes devices and key data converter design. It is delivered with an extensive documentation that, among others, includes Product Brief, User Manual, Verification Guide, Regression Test Environment, Test Cases and test reports.

The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you

wtfdivi014-url15

Proven Quality

Solid process and predictability

Strong verification

agsdi-time

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

Related material

Scroll Up