JESD204B
Overview
The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b10b encoding. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
Learn more about the JESD204 (the history, use cases and common pit falls) by viewing our webinar.
Block Diagram
Key Features
Delivering Performance
- Designed to JEDEC JESD204B specification
- Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 25 Gbps)
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Checks link configuration data with user selected parameter values during initial lane synchronization sequence
- 8b 10b encoding
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1, and 2) on the 8b10b link layer
Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of SerDes PHY solutions
Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Applications
High speed data acquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
We understand Your integration pain
Having supported over 50 customers in integrating JESD204 we understand the key pain area is PHY integration. We have a multi-tier solution to meet your specific needs.
PHY Integration Guide
Access to all Comcores PHY integration expertise in a comprehensive and user-friendly PDF guide, designed to facilitate a clear understanding of crucial hurdles and pitfalls encountered during PHY integration.
PHY Integration Guide with Support Hours
Get an additional 20 hours of support directly from Comcores engineers, to ask integration-related queries. This support can be accessed through our support portal or potentially via live meetings.
PHY Integration Guide with Support Hours & Integration Services
In addition to providing a comprehensive PDF guide and expert guidance, Comcores’ engineers will undertake the PHY integration efforts themselves.
Off the Shelf PHY Integrated Package
Comcores offers an off-the-shelf solution for select PHY models, comprising a pre-integrated package of JESD204 IP with the PHY, that is readily available for instantiation in your project.
Additionally we help our customers with:
- JESD204 Standard Training – to help our customers quickly get up to speed with the JESD204 Standard
- JESD204 Configuration setup – through our Web GUI you can quickly visualize and configure JESD204 Protocol
- Internal Protocol Analysis – Specialized RTL block to help debug problems post system deployment
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Items available for purchase
- UVM VIP
- HW Validation Platform
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Predictions and expectations of the upcoming JESD204D standard
Morten Kofoed Esbjørn - May 2, 2023.JESD204 Standard which was first introduced in 2006 is one of the key standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) and has come a long way since its introduction, evolving with multiple iterations from JESD204B to JESD204C. The latest iteration of this standard the JESD204D is expected to release in Q4 2023 and if you are curious about the latest developments expected in the JESD204 standard, then...
JESD204D Webinar: Expert insights into what we Expect and how to Prepare for the upcoming Standard
Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based our experience working with JESD204. Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward...
What is interlaken?
Morten Kofoed Esbjørn - Oct 31, 2022. Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the...