Overview

The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b 10b encoding. The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.

The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.

Learn more about the JESD204 (the history, use cases and common pit falls) by viewing our webinar.

Block Diagram

Comcores JESD204B diagram

Key Features

Delivering Performance

  • Designed to JEDEC JESD204B specification
  • Line rates from 1 Gbps to 12.5 Gbps (with optional extension to 25 Gbps)
  • Supports 1-24 lanes
  • Supports 1-96 converters
  • HD-mode supported
  • Performs user-enabled scrambling
  • Generates initial lane alignment sequence
  • Performs the alignment character generation
  • Checks link configuration data with user selected parameter values during initial lane synchronization sequence
  • 8b 10b encoding
  • Verilog-based
  • Optional data mapping and de-mapping
  • Supports Subclasses (0, 1, and 2) on the 8b10b link layer

Interoperability

  • JESD204B IP has been interoperability tested with a variety of data converters
  • JESD204B IP has been interoperability tested with key providers of SerDes PHY solutions

Easy to use

  • HW demonstration platform available
  • VIP and regression test suite available
  • SerDes interoperability with several major vendors
  • Simple test bench is included

Silicon Agnostic

  • Designed in Verilog and targeting both ASICs and FPGAs

Applications

High speed data acquisition systems

  • Wireless infrastructure transceiver architectures
  • Radar systems
  • Software-defined radios
  • Portable instrumentation
  • Medical ultrasound equipment

We understand Your integration pain

Having supported over 50 customers in integrating JESD204 we understand the key pain area is PHY integration. We have a multi-tier solution to meet your specific needs.

MACsec vs IPsec

PHY Integration Guide

Access to all Comcores PHY integration expertise in a comprehensive and user-friendly PDF guide, designed to facilitate a clear understanding of crucial hurdles and pitfalls encountered during PHY integration.

MACsec vs IPsec

PHY Integration Guide with Support Hours

Get an additional 20 hours of support directly from Comcores engineers, to ask integration-related queries. This support can be accessed through our support portal or potentially via live meetings.

MACsec vs IPsec

PHY Integration Guide with Support Hours & Integration Services

In addition to providing a comprehensive PDF guide and expert guidance, Comcores’ engineers will undertake the PHY integration efforts themselves.

Tier 4: Off the shelf solution

Off the Shelf PHY Integrated Package

Comcores offers an off-the-shelf solution for select PHY models, comprising a pre-integrated package of JESD204 IP with the PHY, that is readily available for instantiation in your project.

Additionally we help our customers with:

  • JESD204 Standard Training – to help our customers quickly get up to speed with the JESD204 Standard
  • Internal Protocol Analysis – Specialized RTL block to help debug problems post system deployment

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers.
  • Test Report (optional)
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Items available for purchase

  • UVM VIP
  • HW Validation Platform

JESD204 Content

Related Products

What Comcores IP will do for you

R

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

Comcores JESD204D IP core conforming to the Revision D of the JESD204 standard released in Dec’2023 now available

Press Release Copenhagen, Denmark, Jan 8, 2024 - At Comcores we want to keep enabling our customers with the latest IPs and to meet this requirement, for a major part of the last year we have been working on developing our JESD204D IP which was designed based on our understanding of the how the needs of the serialized interface between data converters and logic devices will evolve and a premption of what the JEDEC standards committee would consider as part of the upcoming D revision to the...

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Comcores Unveils JESD204 IP Core Integration Guide to Streamline Customer PHY Integration Challenges

Press Release Copenhagen, Denmark, June 27, 2023 - Through our global leadership within JESD204 IP, Comcores has recognized the challenges faced by customers when integrating the PHY (Physical Layer) with JESD204 IP cores. Having partnered with over 50 customers on various JESD204 projects, Comcores understands the complexity and associated pains involved in this process. Comcores wants to share our learnings for the benefit of our customers. Therefore, Comcores introduces a new...

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