JESD204B
Overview
The JESD204B controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204B.01 serial interface standard targeting both ASICs and FPGAs. The solution by default provides line-speeds of up to 12.5 Gbps per lane while guaranteeing data alignment and synchronization. The standard allows it to optionally by used up to 16 Gbps, but does not recommend running it faster due to the 8b10b encoding.
The core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
Learn more about the JESD204 standard.
Block Diagram
Key Features
Delivering Performance
- Designed to JEDEC JESD204B specification
- Line rates from 1 Gb/s to 12.5 Gb/s (with optional extension to 25 Gb/s)
- Supports 1-24 lanes
- Supports 1-8 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Sources link configuration data with user selected parameter values during initial lane synchronization sequence
- Performs 8b10b encoding
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses 0, 1, and 2
- Internal clock generation
Interoperability
- JESD204B IP has been interoperability tested with a variety of data converters
- JESD204B IP has been interoperability tested with key providers of SerDes PHY solutions
Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Applications
High speed data acquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Please contact us to discuss your project requirements.
Items available for purchase
- UVM VIP
- HW Validation Platform
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Comcores Webinar: “Bridging Analog and Digital worlds at high speed with the JESD204 serial interface”
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
Piotr Koziuk Jan 13 2022 To meet the increased demand for converter speed and resolution, JEDEC proposed the JESD204 standard describing a new efficient serial interface to handle data converters. In 2006, the JESD204 standard offered support for multiple data converters over a single lane with the following standard revisions; A, B, and C successively adding features such as support for multiple lanes, deterministic latency, and error detection and correction while constantly increasing Lane...
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