Overview

The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.

The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.

Learn more about the JESD204 standard.

Block Diagram

JESD204 diagram

Key Features

Delivering Performance

  • Designed to JEDEC JESD204C.1 specification
  • Line rates from 1 Gb/s to 32.5 Gb/s
  • Supports 1-24 lanes
  • Supports 1-32 converters
  • HD-mode supported
  • Performs user-enabled scrambling
  • Generates initial lane alignment sequence
  • Performs the alignment character generation
  • Sources link configuration data with user selected parameter values during initial lane synchronization sequence
  • 8b10b, 64b66b, 64b80b encoding/decoding supported
  • Verilog-based
  • Optional data mapping and de-mapping
  • Supports Subclasses 0, 1, and 2
  • Internal clock generation

Interoperability

  • JESD204C IP has been interoperability tested with Analog Devices JESD204C implementation

Easy to use

  • HW demonstration platform available
  • VIP and regression test suite available
  • SerDes interoperability with several major vendors
  • Simple test bench is included

Silicon Agnostic

  • Designed in Verilog and targeting both ASICs and FPGAs

Applications

High speed data acquisition systems

  • Wireless infrastructure transceiver architectures
  • Radar systems
  • Software-defined radios
  • Portable instrumentation
  • Medical ultrasound equipment

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers.
  • Test Report (optional)
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Items available for purchase

  • UVM VIP
  • HW Validation Platform

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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