JESD204C
Overview
The JESD204C controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 serial interface standard targeting both ASICs and FPGAs. The IP core supports line speeds up to 32.5 Gbps per lane with 64b66b encoding and includes full backwards compatibility with JESD204B and its 8b10b encoding. The IP core enables quick and reliable deployment of both the transmitter (TX) and the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested with key Data Converter ADC/DAC providers and leading SerDes PHY solutions.
Learn more about the JESD204 (the history, use cases and common pit falls) by viewing our webinar.
Block Diagram
Key Features
Delivering Performance
- Designed to JEDEC JESD204C.1 specification
- Line rates from 1 Gbps to 32.5 Gbps
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs user-enabled scrambling
- Generates initial lane alignment sequence
- Performs the alignment character generation
- Checks link configuration data with user selected parameter values during initial lane synchronization sequence
- 8b 10b, 64b 66b, 64b 80b encoding/decoding supported
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1, and 2) on the 64b66b link layer
Interoperability
- JESD204C IP has been interoperability tested with Analog Devices JESD204C implementation
Easy to use
- HW demonstration platform available
- VIP and regression test suite available
- SerDes interoperability with several major vendors
- Simple test bench is included
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Applications
High speed data acquisition systems
- Wireless infrastructure transceiver architectures
- Radar systems
- Software-defined radios
- Portable instrumentation
- Medical ultrasound equipment
We understand Your integration pain
Having supported over 50 customers in integrating JESD204 we understand the key pain area is PHY integration. We have a multi-tier solution to meet your specific needs.
PHY Integration Guide
Access to all Comcores PHY integration expertise in a comprehensive and user-friendly PDF guide, designed to facilitate a clear understanding of crucial hurdles and pitfalls encountered during PHY integration.
PHY Integration Guide with Support Hours
Get an additional 20 hours of support directly from Comcores engineers, to ask integration-related queries. This support can be accessed through our support portal or potentially via live meetings.
PHY Integration Guide with Support Hours & Integration Services
In addition to providing a comprehensive PDF guide and expert guidance, Comcores’ engineers will undertake the PHY integration efforts themselves.
Off the Shelf PHY Integrated Package
Comcores offers an off-the-shelf solution for select PHY models, comprising a pre-integrated package of JESD204 IP with the PHY, that is readily available for instantiation in your project.
Additionally we help our customers with:
- JESD204 Standard Training – to help our customers quickly get up to speed with the JESD204 Standard
- JESD204 Configuration setup – through our Web GUI you can quickly visualize and configure JESD204 Protocol
- Internal Protocol Analysis – Specialized RTL block to help debug problems post system deployment
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Please contact us to discuss your project requirements.
Items available for purchase
- UVM VIP
- HW Validation Platform
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
JESD204 Webinar: “Bridging Analog and Digital worlds at high speed with the JESD204 serial interface”
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
Piotr Koziuk - Jan 13, 2022. To meet the increased demand for converter speed and resolution, JEDEC proposed the JESD204 standard describing a new efficient serial interface to handle data converters. In 2006, the JESD204 standard offered support for multiple data converters over a single lane with the following standard revisions; A, B, and C successively adding features such as support for multiple lanes, deterministic latency, and error detection and correction while constantly increasing...
Interlaken IP Core for high-speed chip-to-chip applications is available
Press Release Copenhagen, Denmark, September 29, 2021 - Comcores ApS, a fast-growing specialized supplier of Intellectual Property (IP) Cores expands its Chip-to-chip Interface IP portfolio by announcing the availability of a high-performance Interlaken IP. Comcores as the leading provider of silicon-proven JESD204B and JESD204C Controller IPs, now introduces a high-performance Interlaken IP, a silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting any ASIC or...