JESD204D
Overview
The JESD204 controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 and JESD204B.01 standard serial interface targeting both ASICs and FPGAs.
The standard for JESD204D is expected to be published late Q1 2023. Comcores is offering an early adapters version of the upcoming JESD204D Controller IP, which will be optimized for the new standard. The upcoming JESD204 IP core is expected to supports line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ, and includes full backwards compatibility with 32.5 Gbps JESD204C.1 64b66b link layer and 16 Gbps JESD204B 8b10b link layer.
The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing.
Learn more about the JESD204 standard.
Block Diagram
Key Features
Richly Featured
- Line rates up to 116 Gbps
- Supports 1-24 lanes
- Supports 1-96 converters
- HD-mode supported
- Performs standard required scrambling
- RS-FEC (544,514), RS-FEC (528,514), RS-FEC (272,258), FEC (144,130) and FEC (136,130)
- Verilog-based
- Optional data mapping and de-mapping
- Supports Subclasses (0, 1 and 3)
Easy to use
- Solid documentation including integration guide
- Easy to use RTL test environment
- Strong engineering support for bring-up
Solid
- Silicon proven
- Lint/CDC optimized
- UVM regression tested
- Interoperability tested with leading PHY/SerDes vendors
Silicon Agnostic
- Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers
- Test Report (optional)
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Please contact us to discuss your project requirements.
Items available for purchase
- UVM VIP
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
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