Overview

The JESD204 controller IP is a highly optimized and silicon agnostic implementation of the JEDEC JESD204C.1 and JESD204B.01 standard serial interface targeting both ASICs and FPGAs.

The standard for JESD204D is expected to be published late Q1 2023. Comcores is offering an early adapters version of the upcoming JESD204D Controller IP, which will be optimized for the new standard. The upcoming JESD204 IP core is expected to supports line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ, and includes full backwards compatibility with 32.5 Gbps JESD204C.1 64b66b link layer and 16 Gbps JESD204B 8b10b link layer.

The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer option, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing.

Learn more about the JESD204 standard.

Block Diagram

Comcores JESD204D diagram

Key Features

Richly Featured

  • Line rates up to 116 Gbps
  • Supports 1-24 lanes
  • Supports 1-96 converters
  • HD-mode supported
  • Performs standard required scrambling
  • RS-FEC (544,514), RS-FEC (528,514), RS-FEC (272,258), FEC (144,130) and FEC (136,130)
  • Verilog-based
  • Optional data mapping and de-mapping
  • Supports Subclasses (0, 1 and 3)

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • Strong engineering support for bring-up

Solid

  • Silicon proven
  • Lint/CDC optimized
  • UVM regression tested
  • Interoperability tested with leading PHY/SerDes vendors

Silicon Agnostic

  • Targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers
  • Test Report (optional)
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Please contact us to discuss your project requirements.

Items available for purchase

  • UVM VIP

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

Related material

What is interlaken?

Morten Kofoed Esbjørn Oct 31 2022, Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the...

read more

Unlock your chips full data transfer potential with Interlaken

WHITEPAPER - Unlock your chips full data transfer potential with Interlaken As data consumption grows and chip designs evolve to meet this demand, Interlaken is the ideal high-speed chip-to-chip interface with efficiency, reliability and scalability. Interlaken addresses modern chip-to-chip design challenges System and chip designers are challenged like never before. The continuous growth in data consumption is driving demand for higher speeds and capacities, but designs also need to consume...

read more

Unlock your chips full data throughput potential with Interlaken

Piotr Koziuk Sep 12 2022, Way back in the early 2000's when XAUI was falling short on link flexibility a search for an alternative chip-to-chip data transfer interface with SPI like features, lead Cisco Systems and Cortina System to put forward the proposal for the Interlaken standard. The new standard married the best of XAUI’s serialized data and SPI’s flow control capabilities. To this day the continuous growth in data consumption is driving demand for higher speeds, but also lower...

read more