MIPI RFFE Master IP Core


The MIPI RFFE Master controller IP is a highly optimized and technology agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors, which are considered RFFE Slaves.

It supports up to 15 slaves and 4 masters that can be connected through RFFE bus. This MIPI RFFE Master IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.
The IP-core has been heavily tested in System Verilog random regression environment.

Block Diagram

MIPI RFFE master block diagram

Key Features

Richly Featured

  • Fully compliant with MIPI RFFE v3.1 Specification
  • Supports up to 15 Slaves on a single RFFE bus instance
  • Supports up to 4 Masters on a single RFFE bus instance
  • Supports all RFFE commands
  • Supports Multi-Mainfunctionality
  • Supports wide range of clock frequencies up to maximum 52 MHz

Silicon Agnostic

  • Targeting both ASICs and FPGAs

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up


  • UVM based Verification
  • Lint/CDC checked


The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Basic RTL Test Bench
  • Synthesis Scripts
  • Synopsys Lint and CDC Waivers
  • Synopsys CDC SGDC Files
  • Synopsys Constraint Files

Related Products

What Comcores IP will do for you


Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research


Long-term experience in communication protocols

Expert in executing digital design projects

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