MIPI RFFE Slaves IP Core

Overview

The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors,

which are considered RFFE Slaves. This MIPI RFFE Slave IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.

The IP-core has been heavily tested in System Verilog random regression environment.

Block Diagram

MIPI RFFE slave block diagram

Key Features

Richly Featured

  • Fully compliant with MIPI RFFE v3.1 Specification
  • Supports all RFFE Slave commands
  • Support Standard, Timed and Mappable Triggers
  • Supports all USID Prgramming procedures: 1, 2 and 3
  • Supports wide range of clock frequencies up to maximum 52 MHz
  • Configurable number of type of registers

Silicon Agnostic

  • Targeting both ASICs and FPGAs

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up

Solid

  • UVM based Verification
  • Lint/CDC checked

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Basic RTL Test Bench
  • Synthesis Scripts
  • Synopsys Lint and CDC Waivers
  • Synopsys CDC SGDC Files
  • Synopsys Constraint Files

Related Products

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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