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Ethernet End Station

One End Station family, every speed from 10M to 2.5G — MAC, timing, security and TSN features built in

Overview

The Comcores End Station is a silicon-proven hardware + software subsystem that turns any device into a deterministic Ethernet endpoint — MAC, time synchronisation, protocol gateway and security in one licensable IP core, for ASIC and FPGA.

One family covers everything from a 10M single-pair sensor node to a 2.5G full-TSN controller, with the same deliverables, the same support and the same integration model at every speed.

Complete endpoint subsystem

MAC, Time-of-Day, IEEE 1722 gateway, MACsec and software stack — not a bare MAC.

Silicon-proven, technology independent

SystemVerilog RTL or encrypted netlist, validated in ASIC and FPGA. Functional Safety Ready — ISO 26262 / ASIL aligned.

One family, every speed

10M · 100M · 10–100M · 10M–1000M · 10M–2.5G — pick the speed, keep the architecture.

Software included

802.1AS stack, FreeRTOS / Zephyr / Linux drivers and a complete demonstration system.

Wide Range – One family. 10 Mb/s to 2.5 Gb/s

One architecture, four members — each covering a different slice of the same speed range. The smallest is a single-pair 10M endpoint; the largest reaches deterministic 2.5G with full TSN.

10M 100M 1G 2.5G
10Msensor & edge nodes
single-pair · half-duplex
10M / 100Mfield devices
10 / 100 field links
10M / 100M / 1G / 2.5Ghigh-bandwidth endpoints
cut-through + integrated DMA
10M / 100M / 1G / 2.5G TSNdeterministic TSN backbones
TSN
full TSN · multi-queue

End Station Configurator

Sample configuration of the End Station and its variants for a sense of the range.

Configure your End Station
A Product variant
10Msingle-pair sensor & edge endpoint 10M / 100M10/100 field-device endpoint 10M / 100M / 1G / 2.5G2.5G · cut-through + DMA, no TSN 10M / 100M / 1G / 2.5G TSN2.5G · full TSN feature set
Representative diagram
END STATION Host AXI4 PHY MII MAC10M store & fwdpacket path 802.1AS gPTPtime sync TSN shapers— MACsec802.1AE 1722 gateway— RedundancyFRER · PFC 10BASE-T1SDigPhy
10M End Station
single-pair sensor & edge endpoint
live preview of your build
B Host interface
AXI4 (32-bit)memory-mapped OPEN Alliance SPI10M only
C Port / data interface
MII RMII GMII RGMII SGMII OA-3P AXI-Streamno Ethernet PHY
F TSN traffic management
TAS802.1Qbv CBS802.1Qav Preemption802.1Qbu + 802.3br Qcifiltering & policing FRER802.1CB · RX only PFC802.3 flow control
Priority queues 1 2 4 8
D Timing — 802.1AS
gPTPtiming & sync
E Security & PHY options
MACsec802.1AE · any variant 10BASE-T1S DigPhy10M & 10M/100M
G IEEE 1722-2025 gateway optional · references IEEE 1722-2025
ACF message types NTSCF / TSCF
CANACF_CAN · 9.4.3/4 LINACF_LIN · 9.4.5 I2CACF_I2C · 9.4.16 Byte-Bus9.4.14/15
Other subtypes
CRFclock ref · clause 10 AAFAVTP audio · clause 7
Stream role Listener Talker Both

Endpoint in detail

Overview, block diagram and specifications for your configured endpoint.

A comprehensive, silicon-proven hardware and software solution for the Ethernet edge node.

The End Station Controller contains a Media Access Controller (MAC) at 10M, a Time-of-Day (TOD) system, and an optional MACsec protection block. It interfaces with nearly any microcontroller or embedded processor over SPI or an AXI Memory-Mapped host interface — with cut-through packet handling as configured.

It supports half- and full-duplex operation over standard MII/RMII, implements IEEE 802.1AS with the 802.1ASds amendment for half-duplex, and ships with device drivers, an 802.1AS stack and a complete FreeRTOS-based demonstration system. Delivered as technology-independent SystemVerilog RTL or encrypted netlist for ASIC and FPGA.

Key Capabilities

Integrated MAC
–Half & full-duplex · configurable architecture
Time-of-Day system
–Wall clock, phase adjustment & SFD timestamping
Dual host interface
–SPI (OPEN Alliance MAC-PHY) or AXI4
IEEE 1722 gateway
–Nine peripheral protocols tunnelled over Ethernet
Functional Safety Ready
–ISO 26262 / ASIL aligned
Comprehensive software
–802.1AS stack, FreeRTOS SDK, Linux drivers

A comprehensive hardware and software TSN capable solution for automotive, aerospace and industrial applications.

The 10M/100M/1G/2.5G Ethernet TSN End Station Controller implements Timing & Synchronisation (802.1AS), Traffic Shaping (802.1Qbv TAS, 802.1Qav CBS, 802.1Qat ATS), Frame Preemption (802.1Qbu), Frame Replication & Elimination (802.1CB), Stream Filtering & Policing (802.1Qci), and optional MACsec (802.1AE) — up to 8 traffic classes, each with a dedicated queue.

Standard GMII/RGMII/SGMII and MDIO PHY interfaces; a 32-bit AXI4-Lite configuration bus and a multichannel DMA controller on a memory-mapped AXI4 master port. The IEEE 1722 gateway is available via fused 10M-class controllers. Ships with OS drivers, an 802.1AS stack and a Linux demonstration system.

Key Capabilities

Time-Aware Shaping
–IEEE 802.1Qbv TAS with grandmaster & slave
Credit-Based Shaping
–IEEE 802.1Qav CBS for audio/video streams
Frame Preemption
–IEEE 802.1Qbu for high-priority interruption
Redundancy & policing
–FRER 802.1CB + stream policing 802.1Qci
IEEE 1722 gateway
–Via fused 10M controllers — low-rate protocols
Comprehensive software
–802.1AS stack, OS drivers, Linux system

Block Diagram

The 10M-class controller — switch between its two host interface implementations.
Block diagram — SPI host interface MicroController SPI End Station Controller IP OPEN Alliance SPI Interface IEEE 802.1ASTime Sync MACsec Statistics MDIO MAC 10M PHYT1S · T1L · T

SPI host — compliant with the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification. Representative diagram — simplified, for illustration only.

Block diagram — AXI host interface EmbeddedProcessor AXI End Station Controller IP AXI Host Interface IEEE 802.1ASTime Sync MACsec Mgmt Config MDIO MAC 10M PHYT1S · T1L · T

AXI host — packets over a 32-bit AXI4 port with configuration and status registers. Representative diagram — simplified, for illustration only.

Block diagram — 10M–2.5G TSN End Station EmbeddedProcessor AXI4-Lite AXI-MM Management Configuration Buffer System DMA Engine IEEE 802.1ASTime Synchronization Traffic ShapersTAS · CBS · ATS Frame BufferQueue Mgmt MAC & VLANFiltering Per-Stream Filt.& Policing Statistics · MDIO MACsec · IEEE 1722 gateway (fused 10M controllers) MAC (Preemptive) 10M–2.5G PHYGMII·RGMII·SGMII

Simplified architecture — the full diagram with all interfaces and options is available in the datasheet. Representative diagram — simplified, for illustration only.

Technical Specifications

Values in teal reflect the configuration — this is the brief specification of configured endpoint.

Ports & PHY interface

Ethernet port1 × 10M, half- and full-duplex
PHY support10BASE-T1S, T1L, T
PHY interfaceStandard MII / RMII · built-in MDIO controller
Packet architectureCut-through
D-PHYNot included

Host Interface

SelectedAXI4-Lite (slave)
SPI optionOPEN Alliance 10BASE-T1x MAC-PHY Serial Interface
Packet handlingSimultaneous TX + RX

Timing & TSN

TSN functionsNone selected
Time sourceTop-level ToD interface (system-provided)
TimestampingEnd of SFD on MII/RMII, or PHY-sourced indication

Gateway & Security

IEEE 1722None selected
MACsecNot included
RCPNot included

Software & Resource Utilization

Operating SystemFreeRTOS / Zephyr / Linux · IEEE 802.1AS software stack
FPGA / ASICAvailable on request — contact Comcores for characterisation data

Ports & PHY interface

Port speed10M / 100M / 1G / 2.5G — one multi-speed port
PHY interfaceGMII, RGMII, SGMII, MDIO · built-in MDIO controller

TSN & traffic management

Selected functions—
Traffic classesUp to 8 per port, each with a dedicated queue
Time sourceTop-level ToD interface (system-provided)

Host integration, Gateway & Security

Host interfaceAXI4-Lite (config) + AXI4 master (multichannel DMA)
IEEE 1722None selected — via fused 10M controllers; low-rate protocols
MACsecNot included
RCPNot included

Software & Resource Utilization

Software stack802.1AS stack, device drivers for several Operating Systems
FPGA / ASICAvailable on request — contact Comcores for characterisation data

Technical Support & Deliverables

Identical across the whole family — every speed, every configuration.

Access to JIRA support system and direct engineer support are part of our support package to help customers during their development and integration phases.

  • Bespoke RTL as source code or encrypted code
  • Solid documentation, including User Manual and Release Note
  • Simulation Environment, including Testbed, Test cases and Test Script
  • Programming Register Specification
  • Timing Constraints in Synopsys SDC format
  • Synopsys SGDC Files (optional) · Synopsys Lint, CDC and Waivers (optional)

Omni500 – Configurable evaluation and prototyping platform

The Omni500 is a configurable evaluation and prototyping platform for deterministic Ethernet systems from 10 Mb/s to 1 Gb/s. It combines TSN networking, multi-speed Ethernet interfaces, and field buses into one compact platform for validation, development, and system integration.

Omni500 is built on combining an AMD Artix UltraScale+ FPGA, Linux-capable control processor, and a comprehensive set of interfaces.

Built for engineers who need deterministic results. The platform handles all real-time packet processing and timestamping in hardware, while the Linux control layer provides the flexibility of a full software stack — Web GUI, REST API, and SDK included.

Omni500 Product image

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Blogs & Whitepapers

Understanding MACsec and Its Integration

Understanding MACsec and Its Integration

Introduction MACsec, as defined by the IEEE 802.1AE standard, provides protection for traffic passing over Layer 1 and Layer 2 links. It is designed to prevent a range of security threats, including man-in-the-middle attacks, pasive wiretapping, impersonation, and...

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