Ethernet End Station
One End Station family, every speed from 10M to 2.5G — MAC, timing, security and TSN features built in
Overview
The Comcores End Station is a silicon-proven hardware + software subsystem that turns any device into a deterministic Ethernet endpoint — MAC, time synchronisation, protocol gateway and security in one licensable IP core, for ASIC and FPGA.
One family covers everything from a 10M single-pair sensor node to a 2.5G full-TSN controller, with the same deliverables, the same support and the same integration model at every speed.
Complete endpoint subsystem
MAC, Time-of-Day, IEEE 1722 gateway, MACsec and software stack — not a bare MAC.
Silicon-proven, technology independent
SystemVerilog RTL or encrypted netlist, validated in ASIC and FPGA. Functional Safety Ready — ISO 26262 / ASIL aligned.
One family, every speed
10M · 100M · 10–100M · 10M–1000M · 10M–2.5G — pick the speed, keep the architecture.
Software included
802.1AS stack, FreeRTOS / Zephyr / Linux drivers and a complete demonstration system.
Wide Range – One family. 10 Mb/s to 2.5 Gb/s
One architecture, four members — each covering a different slice of the same speed range. The smallest is a single-pair 10M endpoint; the largest reaches deterministic 2.5G with full TSN.
End Station Configurator
Sample configuration of the End Station and its variants for a sense of the range.
Endpoint in detail
A comprehensive, silicon-proven hardware and software solution for the Ethernet edge node.
The End Station Controller contains a Media Access Controller (MAC) at 10M, a Time-of-Day (TOD) system, and an optional MACsec protection block. It interfaces with nearly any microcontroller or embedded processor over SPI or an AXI Memory-Mapped host interface — with cut-through packet handling as configured.
It supports half- and full-duplex operation over standard MII/RMII, implements IEEE 802.1AS with the 802.1ASds amendment for half-duplex, and ships with device drivers, an 802.1AS stack and a complete FreeRTOS-based demonstration system. Delivered as technology-independent SystemVerilog RTL or encrypted netlist for ASIC and FPGA.
Key Capabilities
A comprehensive hardware and software TSN capable solution for automotive, aerospace and industrial applications.
The 10M/100M/1G/2.5G Ethernet TSN End Station Controller implements Timing & Synchronisation (802.1AS), Traffic Shaping (802.1Qbv TAS, 802.1Qav CBS, 802.1Qat ATS), Frame Preemption (802.1Qbu), Frame Replication & Elimination (802.1CB), Stream Filtering & Policing (802.1Qci), and optional MACsec (802.1AE) — up to 8 traffic classes, each with a dedicated queue.
Standard GMII/RGMII/SGMII and MDIO PHY interfaces; a 32-bit AXI4-Lite configuration bus and a multichannel DMA controller on a memory-mapped AXI4 master port. The IEEE 1722 gateway is available via fused 10M-class controllers. Ships with OS drivers, an 802.1AS stack and a Linux demonstration system.
Key Capabilities
Block Diagram
SPI host — compliant with the OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface specification. Representative diagram — simplified, for illustration only.
AXI host — packets over a 32-bit AXI4 port with configuration and status registers. Representative diagram — simplified, for illustration only.
Simplified architecture — the full diagram with all interfaces and options is available in the datasheet. Representative diagram — simplified, for illustration only.
Technical Specifications
Ports & PHY interface
Host Interface
Timing & TSN
Gateway & Security
Software & Resource Utilization
Ports & PHY interface
TSN & traffic management
Host integration, Gateway & Security
Software & Resource Utilization
Technical Support & Deliverables
Access to JIRA support system and direct engineer support are part of our support package to help customers during their development and integration phases.
- Bespoke RTL as source code or encrypted code
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Testbed, Test cases and Test Script
- Programming Register Specification
- Timing Constraints in Synopsys SDC format
- Synopsys SGDC Files (optional) · Synopsys Lint, CDC and Waivers (optional)
Omni500 – Configurable evaluation and prototyping platform
The Omni500 is a configurable evaluation and prototyping platform for deterministic Ethernet systems from 10 Mb/s to 1 Gb/s. It combines TSN networking, multi-speed Ethernet interfaces, and field buses into one compact platform for validation, development, and system integration.
Omni500 is built on combining an AMD Artix UltraScale+ FPGA, Linux-capable control processor, and a comprehensive set of interfaces.
Built for engineers who need deterministic results. The platform handles all real-time packet processing and timestamping in hardware, while the Linux control layer provides the flexibility of a full software stack — Web GUI, REST API, and SDK included.
Ethernet TSN Bridge
Complete subsystem that combines a TSN capable Ethernet switch, DMA engine and IEEE 802.1AS time synchronisation.
Ethernet Controller
High-performance Ethernet connectivity for scalable, low-latency networking applications.
Zonal Controller
Automotive TSN IP with Ethernet switching, Root of Trust, and IEEE 1722 support.
Blogs & Whitepapers
Accelerate time-to-market with Ethernet TSN solutions using Comcores IP
Ever since its introduction in 1973, the Ethernet protocol has expanded and evolved to support every conceivable connectivity application. Ethernet is designed to be a non-deterministic packet-based network, but this also means that Ethernet cannot satisfy the needs...