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Ethernet MAC & PCS 10G/25G

Overview

Comcores 10G/25G Ethernet MAC and PCS is a silicon agnostic implementation of the IEEE 802.3 Ethernet Layer 2 and PCS layer. The IP core performs the Link function of the 10G/25G Ethernet Standard and 

is a low latency cut-through or store-and-forward implementation reaching best in market results while still keeping size at a minimum. The core is richly featured, fully configurable and supports IEEE1588.

Block Diagram

Block Diagram of Comcores Ethernet MAC & PCS 10G 25G IP

Key Features

Richly Featured

  • Deficit Idle Count for maximum data throughput
  • Comprehensive statistics gathering
  • Supports VLAN and jumbo frames as an option

Silicon Agnostic

  • Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs

Delivering Performance

  • Designed to IEEE 802.3-2018 specification
  • Ultra low latency and compact implementation

Highly Configurable

  • 10G/25G data rates with cut-through supported
  • Support for IEEE 1588

Deliverables

The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The product comes with Timing Constraints in Synopsys SDC format and Basic RTL Test bench. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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