Overview

Ethernet MAC 40G/100G IP is a solution that enables the client to communicate data using the IEEE 802.3 standard for 40G/100G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is a 128 bit AXI-S and the Ethernet MAC IP comes with 128 bit XLGMII or CGMII interface on the PHY side.

The Ethernet MAC IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is pre-pared for easy integration with  Ethernet PCS 40G/ 100G IP from Comcores. 

Block Diagram

Technical Specifications

Key Features & Benefits

Delivers Performance

• Designed to IEEE 802.3-2018 specification
• Low latency and compact implementation
• Full duplex Ethernet interfaces

Feature Rich

• Deficit Idle Count for maximum data throughput supported
• FCS generation supported
• Optional statistics gathering
• Jumbo frames support
• Easy integration with standard AXI4-Lite control interface or APB
• Promiscuous and non-promiscuous mode
• Optional MDIO interface

Highly Configurable

• 128-bits AXI-Stream interface
• Comes with XLGMII or CGMII as default PHY interface
• 40G/100G data rates with cut-through operation mode, store and forward is optional
• Can be delivered with IEEE 1588 and/or 40G/100G PCS

Silicon Agnostic

• Designed in SystemVerilog and targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual and Release Note
• Simulation Environment, including Simple Testbed, Test case and Test Script
• Programming Register Specification
• Timing Constraints in Synopsys SDC format
• Access to support system and direct support from Comcores Engineers
• Synopsys SGDC Files (optional)
• Synopsys Lint, CDC and Waivers (optional)