Overview

Comcores TSN MAC 40G/100G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Pre-emption and 802.3br Interspersing Express Traffic. This enables the use of the MAC in high-speed time-critical applications. The MAC-core performs the Link function of the 40G/100G Ethernet Standard and is a low latency cut-through implementation, while keeping size at a minimum.

The core is fully configurable, interfaces easily to standard 40G/100G PCS due to its CGMII interface and can optionally include IEEE 1588 Timestamping Unit (TSU). The Ethernet MAC Core, on the Client side, implements a 256-bit AXI-Stream interface for Express and Preemptable traffic respectively while having a standard 256-bit CGMII interface on the PHY side. 

Block Diagram

Technical Specifications

Key Features & Benefits

Delivers Performance

• Designed to IEEE 802.3-2018 specification
• Supports 802.1 Qbu and 802.3 br with extensions available
• Ultra low latency and compact implementation
• Full duplex Ethernet interfaces

Feature Rich

• Deficit Idle Count for maximum data throughput supported
• In-Band FCS supported
• Supports Link verification, jumbo frames and many other options
• Independent TX and RX Maximum Transmission Unit (MTU)
• Optionally comprehensive statistics gathering
• Easy integration with standard AXI4 lite or APB interface
• IEEE 802.3br (Interspersing Express Traffic) Supported
• IEEE 802.1Qbu (Frame Preemption) supported
• IEEE 802.1CM (Time-Sensitive Networking for Fronthaul) supported
• IEEE 802.1Qbv (Enhancements for scheduled traffic)
• IEEE 802.1CB (Frame Replication and Elimination for Reliability)
• IEEE 802.1AS (Timing and Synchronization)
• IEEE 1588 (Precision Time Protocol, PTP)

Highly Configurable

• 128 bit low latency Ethernet MAC
• 40G/100G data rates with cut-through supported
• TSN features can be enabled/disabled independently
• Timestamping Unit with 802.1 AS extension available

Silicon Agnostic

• Designed in SystemVerilog and targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual and Release Note
• Simulation Environment, including Simple Testbed, Test case and Test Script
• Programming Register Specification
• Timing Constraints in Synopsys SDC format
• Access to support system and direct support from Comcores Engineers
• Synopsys SGDC Files (optional)
• Synopsys Lint, CDC and Waivers (optional)