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Ethernet PCS

200G/400G

Size optimized, Silicon agnostic, Silicon Proven Ethernet PCS IP core for High Speed Ethernet applications

Overview
Block Diagram
Specifications
Deliverables
Related Products

Overview

The 200G/400G Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2020 and its compliant with Clause 117 and Clause 119 of IEEE 802.3 specification.

Ethernet PCS 200G/400G   IP from Comcores provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 8 or 16-lane parallel interface and offers a 200GMII or 400GMII interface on the other side.

Comcores 200G/400GEthernet PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast-track any project.

The 200G/400G Ethernet PCS IP supports 200G or 400G line rates, however, other Ethernet PCS speeds are also available, including the 100G Ethernet PCS and 800G Ethernet PCS.

Block Diagram

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Technical Specifications

Key Features & Benefits

Delivers Performance

  • Supports Ethernet speed of 200G or 400G
  • Complete 200GBASE-R or 400GBASE-R with RS-FEC solution
  • Can be used in common 200G/400G Ethernet PHY applications

Feature Rich

  • Configurable for several operating modes and speeds
  • Works with multiple SerDes widths
  • Clause 117 Reconciliation Sublayer (RS) and Media Independent Interface for 200 Gb/s and 400 Gb/s operation (200GMII and 400GMII)
  • Clause 119 Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R, and 400GBASE-R
  • Clause 45 Management Data Input/Output (MDIO) Interface
  • 64B/66B encoding/decoding
  • Time Synchronization can optionally be included

Highly Configurable

  • BUS2IP is the default Slave PHY Management interface, with AXI, APB, MDIO being optional
  • Easy interfacing to standard MACs
  • Several common control bus standards are supported
  • Can be delivered with integrated MAC for plug and play
  • Includes test pattern Generator/Checker

Silicon Agnostic

  • Designed in SystemVerilog and targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note
  • Simulation Environment, including Simple Testbed, Test case and Test Script
  • Programming Register Specification
  • Timing Constraints in Synopsys SDC format
  • Access to support system and direct support from Comcores Engineers
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)