Ethernet MAC 10M/100M/1G/2.5G
Overview
Comcores Ethernet MAC 10M/100M/1G/2.5G IP solution is providing the link function of the IEEE 802.3 for the respective speeds. Features a compact and low latency solution.
The core is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The core is prepared for easy interfacing with Comcores PCS 10M/100M/1G/2.5G IP solution.
Block Diagram
Key Features
Delivers Performance
- Designed to IEEE 802.3-2018 specification
- Low latency and compact implementation
- Full duplex Ethernet interfaces
Feature Rich
- FCS generation and jumbo frames supported
- Optional comprehensive statistics gathering
- Independent TX and RX Maximum Transmission Unit (MTU) frame length
Highly Configurable
- 8-bits AXI-Stream interface
- Cut-through operation mode
- Optional IEEE 1588 Support
- Comes with GMII as default PHY interface – MII and RGMII can be optionally selected
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Comcores TSN technology and 5G communication expertise to be deployed in a significant EU funded project with pan-European partners
Morten Kofoed Esbjørn - Jan 20, 2023. The OCTAPUS initiative is an EU funded project, which started in September 2022 and is funded until February 2026. OCTAPUS stands for “Optical Circuit switched Time-Sensitive Network (TSN) architecture for highspeed Passive optical networks and next generation Ultra-dynamic & reconfigurable central office environments”, and the goal is to deliver an agile, low-cost and energy efficient Photonic Integrated Circuit (PIC) technology framework. OCTAPUS was...
O-RAN Fronthaul Security using MACsec
WHITEPAPER - O-RAN Fronthaul Security using MACsec With 5G being deployed for time-sensitive applications, security is becoming an important consideration. At the same time, Open Radio Access Networks (RAN) are gaining more interest from mobile carriers and governments. Yet, Open RAN networks have serious security challenges, especially in the RAN fronthaul where there are strict timing requirements. This paper proposes MACsec as an efficient data link layer security solution that can assist...
MACsec for Deterministic Ethernet applications
WHITEPAPER - MACsec for Deterministic Ethernet applications Why MACsec is a compelling security solution for Deterministic Ethernet networks and how Packaged Intellectual Property solutions can accelerate time-to-market for chip developers. Security has long been a top priority in communications networks. However, networks that support time-sensitive applications face challenges in implementing adequate security mechanisms that also meet latency and jitter requirements. This includes networks...