Ethernet TSN MAC 10G/25G
Overview
Comcores TSN MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and 802.3br Interspersing Express Traffic. This enables the use of the MAC in high speed time-critical applications.
The MAC-core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation, while keeping size at a minimum.
The core is fully configurable and interfaces easily to 10G/25G PCS, and can optionally include IEEE 1588 Timestamping Unit (TSU).
The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard 64-bit XGMII interface on the PHY side.
Block Diagram
Key Features
Richly Featured
- Deficit Idle Count for maximum data throughput supported
- In-Band FCS supported
- Supports Link verification, jumbo frames and many other options
- Independent TX and RX Maximum Transmission Unit (MTU)
- Optionally comprehensive statistics gathering
- Easy integration with standard AXI4 lite or APB interface
- IEEE 802.3br (Interspersing Express Traffic) Supported
- IEEE 802.1Qbu (Frame Preemption) supported
- IEEE 802.1CM (Time-Sensitive Networking for Fronthaul) supported
Delivers Performance
- Designed to IEEE 802.3-2018 specification
- Supports 802.1 Qbu and 802.3 br with extensions available
- Ultra low latency and compact implementation
- Full duplex Ethernet interfaces
Highly Configurable
- 64-bit low latency Ethernet MAC
- 10G/25G data rates with cut-through supported
- TSN features can be enabled/disabled independently
- Timestamping Unit with 802.1 AS extension available
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case and Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional).
- Synopsys Lint, CDC and Waivers (optional).
Items available for purchase
- IEEE 802.1Qbv (Enhancements for scheduled traffic).
- IEEE 802.1CB (Frame Replication and Elimination for Reliability).
- IEEE 802.1AS (Timing and Synchronization).
- IEEE 1588 (Precision Time Protocol, PTP).
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Webinar on understanding TSN and its use cases for Aviation, Aerospace and Defence
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Morten Kofoed Esbjørn - Jan 20, 2023. The OCTAPUS initiative is an EU funded project, which started in September 2022 and is funded until February 2026. OCTAPUS stands for “Optical Circuit switched Time-Sensitive Network (TSN) architecture for highspeed Passive optical networks and next generation Ultra-dynamic & reconfigurable central office environments”, and the goal is to deliver an agile, low-cost and energy efficient Photonic Integrated Circuit (PIC) technology framework. OCTAPUS was...