Ethernet MAC 10G/25G
Overview
Comcores Ethernet MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution. The MAC IP core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation, while keeping size at a minimum.
The core is highly configurable and easy interfacing with Comcores IEEE 1588 Timestamping Unit (TSU) and 10G/25G PCS solutions.
The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S Client interface while having a standard 64-bit XGMII interface on the PHY side.
Block Diagram
Key Features
Delivers Performance
- Designed to IEEE 802.3-2018 specification
- Ultra low latency and compact implementation
- Full duplex Ethernet interfaces
Feature Rich
- Deficit Idle Count for maximum data throughput supported
- FCS generation supported
- Optional statistics gathering
- Jumbo frames support
- Easy integration with standard AXI4-Lite control interface or APB
Highly Configurable
- Can be delivered with IEEE 1588 and/or PCS
- Can be delivered with statistics gathering or status vectors
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Please contact us to discuss your project requirements.
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Interoperability with AD9152 DAC
Test Reports The Comcores JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) and DAC (digital-to-analog) devices. The purpose of this document is to provide the reader with detailed understanding of how the Inter-Operability Testing (IOT) between Comcores JESD204B IP core and Analog Devices AD9152 DAC has been carried out....
Comcores 10G TSN Ethernet MAC solution is available
Press Release Copenhagen, Denmark, June 2, 2016 — Denmark Headquartered Comcores ApS, a specialized supplier of silicon intellectual property (SIP) today announced the immediate availability of a 10G Time-Sensitive-Networking (TSN) Ethernet MAC solution targeting FPGA and ASIC devices. The TSN-solution supports features like Frame Pre-emption (IEEE 802.3 br and IEEE 802.1 Qbu), Timing and Synchronization (IEEE 802.1 AS) with more to come. The 10G TSN Ethernet MAC makes it possible to generate...
Comcores release a mixed speed 1G and 10G Ethernet Switch
Press Release Comcores provide Flexible Ethernet Switch IP Design Optimized for switching in C-RAN and Next-Generation LTE Advanced Networking Equipment Copenhagen, Denmark, Feb 11, 2016 —Comcores ApS, a leading provider of IP cores for wireless networks today announced immediate availability of an ultra-compact Ethernet Switch IP with support for both 1G and 10G ports. The design includes features like 1588 bypass and VLAN functionality and is suited to deliver on your Ethernet switching...