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DMA Controller

Overview

Comcores multi-channel DMA Controller IP core provides high bandwidth direct memory access between memory and AXI4-Stream or AHB type of IP peripherals for up to 16 channels. The DMA IP includes Scatter-Gather capabilities which help in offloading data movement tasks from the Central Processing Unit (CPU) in processor-based systems.

Configuration of status and management registers are accessed through an AXI4-Lite or AHB slave interface. Control and Status streaming interfaces are used for sending/receiving user application data. Interrupts are available to indicate error and completion events.

Block Diagram

Block Diagram of Comcores DMA IP

Key Features

Richly featured

  • AMBA/AHB and AXI4-Streaming compliant user interface
  • 1–16 independent DMA channels supporting bi-directional data transfers
  • Driver for Linux platform is available

Solid

  • Silicon proven
  • UVM VIP is available

Flexible

  • Scatter-Gather DMA mode enabled
  • Supports Memory-Memory, Memory-Peripheral and Peripheral-Memory

Silicon Agnostic

  • Designed in VHDL and targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Access to support system and direct support from Comcores Engineers.
  • Linux Driver (optional)
  • Synopsys Lint and CDC (optional)

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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