Ethernet MAC & PCS 10G/25G
Overview
Comcores 10G/25G Ethernet MAC and PCS is a silicon agnostic implementation of the IEEE 802.3 Ethernet Layer 2 and PCS layer. The IP core performs the Link function of the 10G/25G Ethernet Standard and
is a low latency cut-through or store-and-forward implementation reaching best in market results while still keeping size at a minimum. The core is richly featured, fully configurable and supports IEEE1588.
Block Diagram
Key Features
Richly Featured
- Deficit Idle Count for maximum data throughput
- Comprehensive statistics gathering
- Supports VLAN and jumbo frames as an option
Highly Configurable
- 10G/25G data rates with cut-through supported
- Support for IEEE 1588
Delivering Performance
- Designed to IEEE 802.3-2018 specification
- Ultra low latency and compact implementation
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
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