Ethernet Packet Switch 1G
Overview
Comcores Ethernet Packet Switch 1G IP core is an advanced switch supporting buffering of large amounts of data in external RAM. The non-blocking Ethernet switch IP core enables fine-grained traffic differentiation for rich implementations of packet prioritization enabling per port and per queue shaping on egress ports.
The switch supports MAC learning, VLAN 802.1Q, multicast and broadcast as well as IEEE 1588 transparency. Each port provides a native interface for GMII Ethernet PHY devices.
Block Diagram
Key Features
Delivers Performance
- QoS features such as classification, queuing and priorities included
- Automatic MAC address learning and aging
- Supports buffering of up to 128 MB in DDR
- Extensive statistic reporting
Easy to use
- Solid Verification Environment
- GMII interfaces for attaching external Physical Layer devices (PHY)
Highly Configurable
- Buffer size fully configurable
- Configurable scheduling (round-robin, strict priority, etc.)
- Configurable tagging
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Access to support system and direct support from Comcores Engineers.
- Synopsys Lint Waivers (optional)
Related Products
Find an Ethernet Switch IP that matches your requirements
Features \ Products
Description
Port Configuration
Number of ports
Port Interface
Frame size
Statistical Counters
VLAN support
Multicast
MAC address learning
MAC address aging
QoS Features
IEEE 1588 Transparent Clock
IEEE 1588 Boundary clock (PTP.v2)
Time Sensitive Networking (TSN) Features
Packet Trapping
Software API
Ethernet Switch 1G
Space Efficient Switch for Embedded Applications
1G
2-36 Ports
GMII
64B - 16384B
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
Ethernet Switch 1G/10G
Space Efficient Switch for Embedded Applications
1G/10G
2-40 (1Gbps Ports) & 0-4 (10Gbps Ports)
64B - 16384B
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
Ethernet Switch 10G
Space Efficient Switch for Embedded Applications
10G
3-20 Ports
64B - 16384B
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
Ethernet Switch 10G/25G
Space Efficient Switch for Embedded Applications
12 (10Gbps Ports) & 4 (25Gbps Ports)
XGMII/XXVMII (10G/25G)
64B - 16384B
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
-
Ethernet Packet Switch 1G
Ethernet Switch with External DDR Packet Buffers
1G
Up to 8 Ports (1G/2.5G speed supported)
GMII
Up to 2048 bytes support
Yes
Yes
Yes
Yes
Yes
Yes
-
-
-
-
-
ETHERNET TSN ADVANCED SWITCH 10M/100M/1G/10G/25G – MANTICORE
Advanced Switch for High Throughput Applications
10M/100M/1G/10G/25G
Up to 64 Ports
AXI4 S/XGMII
64B - 16384B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
Comcores TSN technology and 5G communication expertise to be deployed in a significant EU funded project with pan-European partners
Morten Kofoed Esbjørn - Jan 20, 2023. The OCTAPUS initiative is an EU funded project, which started in September 2022 and is funded until February 2026. OCTAPUS stands for “Optical Circuit switched Time-Sensitive Network (TSN) architecture for highspeed Passive optical networks and next generation Ultra-dynamic & reconfigurable central office environments”, and the goal is to deliver an agile, low-cost and energy efficient Photonic Integrated Circuit (PIC) technology framework. OCTAPUS was...
O-RAN Fronthaul Security using MACsec
WHITEPAPER - O-RAN Fronthaul Security using MACsec With 5G being deployed for time-sensitive applications, security is becoming an important consideration. At the same time, Open Radio Access Networks (RAN) are gaining more interest from mobile carriers and governments. Yet, Open RAN networks have serious security challenges, especially in the RAN fronthaul where there are strict timing requirements. This paper proposes MACsec as an efficient data link layer security solution that can assist...
MACsec for Deterministic Ethernet applications
WHITEPAPER - MACsec for Deterministic Ethernet applications Why MACsec is a compelling security solution for Deterministic Ethernet networks and how Packaged Intellectual Property solutions can accelerate time-to-market for chip developers. Security has long been a top priority in communications networks. However, networks that support time-sensitive applications face challenges in implementing adequate security mechanisms that also meet latency and jitter requirements. This includes networks...