Ethernet PCS 100G

Overview

Comcores PCS 100G IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 82 of IEEE 802.3ba and Clause 91 of IEEE 802.3bj specification.

 

The PCS IP core is part of a family of IP cores that are tightly integrated. The IP core has been optimized for size and offers a CGMII interface on one side and a 4 lane parallel interface at the PMA-side.

Block Diagram

Block Diagram of Comcores Ethernet PCS 10G/25G IP

Key Features

Highly Configurable

  • Configurable for several operating modes and speeds
  • Works with multiple SerDes widths

Delivering Performance

  • Supports Ethernet speed of 100G
  • Complete 100GBASE-R with RS-FEC solution
  • Can be used in common 100G Ethernet PHY applications

Easy to Use

  • Easy interfacing to standard MACs
  • Several common control bus standards are supported
  • Can be delivered with integrated MAC for plug and play
  • Includes test pattern Generator/Checker

Silicon Agnostic

  • Designed in SystemVerilog and targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Programming Register Specification.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers.
  • Synopsys SGDC Files (optional)
  • Synopsys Lint, CDC and Waivers (optional)

Please contact us to discuss your project requirements.

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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