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Ethernet PCS 100G

Overview

Comcores PCS 100G IP core is a silicon agnostic implementation of the PCS layer described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 82 of IEEE 802.3ba and Clause 91 of IEEE 802.3bj specification. The IP-core is part of a family of IP-cores that are tightly integrated.

 

The IP-core has been optimized for size and offers a CGMII interface on one side and a 4 lane 10-66-bit parallel interface at the PMA-side.

Block Diagram

Block Diagram of Comcores Ethernet PCS 10G/25G IP

Key Features

Highly Configurable

  • Configurable for many operating modes and speeds
  • Works with multiple Serdes widths

Delivering Performance

  • Supports Ethernet speed of 100G
  • Complete 100GBASE-R with RS-FEC solution
  • Can be used in common 100G Ethernet PHY applications

Easy to Use

  • Easy interfacing to standard MACs
  • Several common control bus standards are supported
  • Can be delivered with integrated MAC for plug and play
  • Includes test pattern Generator/Checker

Silicon Agnostic

  • Designed in System Verilog and targeting any RTL implementation like ASICs, and FPGAs

Deliverables

The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The product comes with Timing Constraints in SDC format. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you

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Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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