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Ethernet PCS 10G/25G

Overview

Comcores 10G/25G PCS IP core is a silicon agnostic implementation of the PCS layer described in the Ethernet standard IEEE 802.3-2015 and compliant with Clause 49 of IEEE 802.3ae specification. The IP-core is part of a family of IP-cores that are tightly intergrated.

 

The IP-core has been optimized for size and offers an XGMII interface on one side and a 64-bit interface at the PMA-side.

Block Diagram

Block Diagram of Comcores Ethernet PCS 10G/25G IP

Key Features

Highly Configurable

  • Configurable for many operating modes and speeds
  • Works with multiple Serdes widths

Delivering Performance

  • Supports Ethernet speeds of 10G and 25G
  • Complete 10GBASE-R and 25GBASE-R PCS solution
  • Can be used in any 10G or 25G Ethernet PHY application 

Silicon Agnostic

  • Designed in VHDL and targeting any RTL implementation like ASICs, ASSPs and FPGAs

Easy to use

  • Easy interfacing to standard MAC’s
  • Several common control bus standards are supported 
  • Can be delivered with integrated MAC for plug and play
  • Includes test pattern Generator/Checker

Applications

Any Ethernet Solution

  • Fits into solutions where Ethernet PCS is needed

Multi-rate solutions

  • Enabling use of multiple rates of Ethernet

Deliverables

The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The product comes with Timing Constraints in Synopsys SDC format. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you

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Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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