Ethernet PCS 10G/25G
Overview
Comcores 10G/25G PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3-2018 and compliant with Clause 49 of IEEE 802.3ae specification.
The IP core is part of a family of IP cores that are tightly integrated. The PCS IP core has been optimized for size and offers an XGMII/XXVGMII/XLGMII interface on one side and a 10-80-bit parallel interface at the PMA-side.
Block Diagram
Key Features
Highly Configurable
- Configurable for several operating modes and speeds
- Works with multiple SerDes widths
Delivering Performance
- Designed to IEEE 802.3-2018
- Supports Ethernet speeds of 10G and 25G
- Complete 10GBASE-R and 25GBASE-R PCS solution
- Can be used in any 10G or 25G Ethernet PHY application
Multi-rate solutions
- Enabling use of multiple rates of Ethernet
Easy to use
- Easy interfacing to standard MAC’s
- Several common control bus standards are supported
- Can be delivered with integrated MAC for plug and play
- Includes test pattern Generator/Checker
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs
Applications
Any Ethernet Solution
- Fits into solutions where Ethernet PCS is needed
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
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