Ethernet PCS 1G/2.5G
Overview
Comcores PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018. The IP core supports 1G and 2.5G line rates. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent Interface (GMII) or Serial Gigabit Media Independent Interface (SGMII).
On one side it interfaces to a SerDes device and on the application side it has a port for GMII/SGMII Ethernet signals.
The PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.
Key Features
Richly Featured
- Configurable for several modes
- IEEE Std. 802.3 Clause 37 Auto-negotiation
- Support GMII interface for 1000BASE-X
- 8B10B encoding to convert data to 10-bit encoded data for each lane
- IEEE Std. 802.3 Clause 37 Auto-negotiation
- Near-end loopback at both ends
Delivering Performance
- Designed to IEEE 802.3-2018 specification
- Low Latency
- Can be used in synchronous Ethernet applications
Easy to use
- AXI/APB/MDIO Slave PHY Management interface
- GMII/SGMII interfaces for attaching to Ethernet MAC
- Solid documentation
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs
Applications
Any 1G/2.5G Ethernet Solution
- Fits into solutions where Ethernet PCS is needed
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
Please contact us to discuss your project requirements.
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Related material
O-RAN Fronthaul Security using MACsec
WHITEPAPER - O-RAN Fronthaul Security using MACsec With 5G being deployed for time-sensitive applications, security is becoming an important consideration. At the same time, Open Radio Access Networks (RAN) are gaining more interest from mobile carriers and governments. Yet, Open RAN networks have serious security challenges, especially in the RAN fronthaul where there are strict timing requirements. This paper proposes MACsec as an efficient data link layer security solution that can assist...
MACsec for Deterministic Ethernet applications
WHITEPAPER - MACsec for Deterministic Ethernet applications Why MACsec is a compelling security solution for Deterministic Ethernet networks and how Packaged Intellectual Property solutions can accelerate time-to-market for chip developers. Security has long been a top priority in communications networks. However, networks that support time-sensitive applications face challenges in implementing adequate security mechanisms that also meet latency and jitter requirements. This includes networks...
O-RAN Fronthaul Transport Security using MACsec
Daniel Dik Sep 14 2022, 5G provides a range of improvements compared to existing 4G LTE mobile networks in regards to capacity, speed, latency and security. One of the main improvements is in the 5G RAN; it is based on a virtualized architecture where functions can be centralized close to the 5G core for economy or distributed as close to the edge as possible for lower latency performance. The functional split options for the baseband station processing chain results in a separation between...