Ethernet PCS 1G/2.5G

Overview

Comcores Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) compliant with Ethernet standard IEEE 802.3-2018. The IP core supports 1G and 2.5G line rates, however other Ethernet PCS speeds are available, such as 10G/25G and 100G. The IP provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a Gigabit Media Independent Interface (GMII) or Serial Gigabit Media Independent Interface (SGMII).

On one side it interfaces to a SerDes device and on the application side it has a port for GMII/SGMII Ethernet signals.

The PCS IP core is verified using advanced methodologies for RTL design, verification, HW verification and interoperability testing. It has been optimized for size and is a highly tested solution that will fast track any project.

Block Diagram

Block Diagram of Comcores Ethernet PCS 1G/2.5G IP

Key Features

Richly Featured

  • Configurable for several modes
  • IEEE Std. 802.3 Clause 37 Auto-negotiation
  • Support GMII interface for 1000BASE-X
  • 8B 10B encoding to convert data to 10-bit encoded data for each lane
  • Near-end loopback at both ends

Delivering Performance

  • Designed to IEEE 802.3-2018 specification
  • Low Latency
  • Can be used in synchronous Ethernet applications

Easy to use

  • AXI/APB/MDIO Slave PHY Management interface
  • GMII/SGMII interfaces for attaching to Ethernet MAC
  • Solid documentation

Silicon Agnostic

  • Designed in VHDL and targeting both ASICs and FPGAs

Applications

Any 1G/2.5G Ethernet Solution

  • Fits into solutions where Ethernet PCS is needed

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case and Test Script.
  • Timing Constraints in Synopsys SDC format.
  • Access to support system and direct support from Comcores Engineers.
  • Synopsys SGDC Files (optional).
  • Synopsys Lint, CDC and Waivers (optional).

Related Products

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

What is TSN?

Morten Kofoed Esbjørn - Feb 14, 2023. TSN, or Time-Sensitive Networking, is a technology based on the IEEE 802.1Q standard. It has evolved from the Ethernet technology currently used to carry all types of traffic, for which ethernet was not originally intended, such as multiple data flows with different timing requirements, commonly found in Audio Video Bridging (AVB), automotive and industrial automation applications. TSN sits in Layer 2 of the OSI Model (figure 1).Figure 1: Illustration of...

read more

Comcores TSN technology and 5G communication expertise to be deployed in a significant EU funded project with pan-European partners

Morten Kofoed Esbjørn - Jan 20, 2023. The OCTAPUS initiative is an EU funded project, which started in September 2022 and is funded until February 2026. OCTAPUS stands for “Optical Circuit switched Time-Sensitive Network (TSN) architecture for highspeed Passive optical networks and next generation Ultra-dynamic & reconfigurable central office environments”, and the goal is to deliver an agile, low-cost and energy efficient Photonic Integrated Circuit (PIC) technology framework. OCTAPUS was...

read more