Ethernet Subsystem 10G/25G
Overview
Comcores Ethernet Subsystem IP is a silicon-agnostic, easy-to-use integration of specific IP blocks. The subsystem IP is richly featured, highly configurable and comes in different variations of Ethernet MAC, Ethernet PCS, IEEE 1588 PTP (with Time Stamping Unit), DMA and can include TSN features.
The subsystem IP is ready for 5G applications, and is thoroughly tested and verified, thus reducing your risks and will save development time as the solution will reduce your design and integration efforts.
Block Diagram
Key Features
Flexible
The Ethernet subsystem consists of various IP blocks that can be selected or
deselected based on customers’ requirements. The main versions are:
01- Ethernet MAC and PCS
02- Ethernet MAC, PCS, and Timestamping Unit (TSU)
03- Ethernet MAC, PCS, and IEEE 1588 PTP (TSU and SW Stack)
04- Ethernet MAC, PCS, IEEE 1588 PTP (TSU and SW Stack), and DMA
*** Ethernet MAC can be replaced by TSN MAC in all versions
5G Ready
- The subsystem has been designed for 5G applications and has been delivered to 5G projects.
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs
Feature Rich
- FCS generation supported
- Deficit Idle Count for maximum data throughput supported
- Jumbo frames support
- Complete 10GBASE-R and 25GBASE-R PCS solution
- Configurable for several operating modes and speeds
- 64b 66b encoding/decoding
- Reconciliation Sublayer (RS) and 10 Gigabit Media Independent Interface (XGMII)
- Two-step messaging by default, with one-step messaging being optional
Ease-to-use and Reliable
- HW validated subsystem
- IP blocks are integrated and tested together
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case and Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- IEEE 1588 PTP SW (optional).
- DMA Driver (optional).
- Synopsys Lint and CDC (optional).
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
Webinar on understanding TSN and its use cases for Aviation, Aerospace and Defence
What is TSN?
Morten Kofoed Esbjørn - Feb 14, 2023. TSN, or Time-Sensitive Networking, is a technology based on the IEEE 802.1Q standard. It has evolved from the Ethernet technology currently used to carry all types of traffic, for which ethernet was not originally intended, such as multiple data flows with different timing requirements, commonly found in Audio Video Bridging (AVB), automotive and industrial automation applications. TSN sits in Layer 2 of the OSI Model (figure 1).Figure 1: Illustration of...
Comcores TSN technology and 5G communication expertise to be deployed in a significant EU funded project with pan-European partners
Morten Kofoed Esbjørn - Jan 20, 2023. The OCTAPUS initiative is an EU funded project, which started in September 2022 and is funded until February 2026. OCTAPUS stands for “Optical Circuit switched Time-Sensitive Network (TSN) architecture for highspeed Passive optical networks and next generation Ultra-dynamic & reconfigurable central office environments”, and the goal is to deliver an agile, low-cost and energy efficient Photonic Integrated Circuit (PIC) technology framework. OCTAPUS was...