Ethernet Subsystem 10G/25G
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Comcores Engineers.
- IEEE 1588 PTP SW (optional)
- DMA Driver (optional)
- Synopsys Lint and CDC (optional)
Please contact us to discuss your project requirements.
What Comcores IP will do for you
Solid process and predictability
First in bringing out new solutions
Tremendous investments in research
Long-term experience in communication protocols
Expert in executing digital design projects
WHITEPAPER Accelerate time-to-market with reliable Ethernet TSN solutions using Comcores IP Ever since its introduction in 1973, the Ethernet protocol has expanded and evolved to support every conceivable connectivity application. Ethernet is designed to be a non-deterministic packet-based network, but this also means that Ethernet cannot satisfy the needs of applications that require time-critical, fail-safe operation. These short-comings are targeted by the Ethernet Time-Sensitive Networking...
Comcores and DENSO AUTOMOTIVE Deutschland GmbH test TSN Ethernet for Automotive Applications in the Research Project EMPHASE
Press Release Comcores and DENSO AUTOMOTIVE Deutschland GmbH test TSN Ethernet for Automotive Applications in the Research Project EMPHASE Copenhagen, Denmark, May 1, 2019 - Denmark Headquartered Com cores ApS, a specialized supplier of silicon intellectual property (SIP) has entered into an agreement supplying DENSO AUTOMOTIVE Deutschland GmbH with time sensitive networking (TSN) Ethernet IP for EMPHASE research project https://www.emphase-projekt.de/index.htmI. The project aims, among...
Test Reports The Comcores JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) and DAC (digital-to-analog) devices. The purpose of this document is to provide the reader with detailed understanding of how the Inter-Operability Testing (IOT) between Comcores JESD204B IP core and Analog Devices AD9152 DAC has been carried out....