Ethernet Switch 10G


Comcores 10G Ethernet Switch IP core is a highly configurable and size optimized implementation of a non-blocking switch that allows continuous transmissions between 10G Ethernet ports. 

The switch supports MAC learning, VLAN 802.1Q, multicast, broadcast, as well as IEEE 1588 transparency. Each port provides a native interface for XGMII Ethernet PHY devices. The switch can optionally be delivered in a TSN version.

Block Diagram

Block Diagram of Comcores Ethernet Switch 10G IP

Key Features

Ultra Compact Size

  • Build to target low size

Delivers Performance

  • Automatic MAC addresses learning and aging
  • Programmable FW operation with Static or Dynamic switching table entries
  • Full duplex Ethernet interfaces
  • Optimized for size

Easy to use

  • XGMII interfaces for attaching external Physical Layer devices (PHY)
  • Very easy integration with standard Xilinx AXI4 Lite control interface
  • Can be used in managed or unmanaged implementations

Highly Configurable

  • Up to 20 ports configurable at compile time
  • Configurable queuing behavior (round-robin, fair queuing, etc.)
  • Support Ethernet Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames
  • Configurable support for 1588 PTP Transparent Clock functionality

Silicon Agnostic

  • Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs


The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you


Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research


Long-term experience in communication protocols

Expert in executing digital design projects

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