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Ethernet Switch 1G

Overview

Comcores Ethernet Switch IP core is a highly configurable and size optimized implementation of a non-blocking ring switch that allows continuous transfers between up to 36 Ethernet ports via 1 Gbps GMII interfaces. The switch supports MAC learning and implements store-and-forward switching approach in order to fulfill Ethernet standard policy regarding frame integrity checking.

The 1G Ethernet Switch IP core supports up to 36 ports where each port provides GMII native interface for Ethernet PHY devices.

The number of ports are configurable at compile time.

Block Diagram

Ethernet Switch 1G Block Diagram

Key Features

Delivers Performance

  • Automatic MAC addresses learning
  • Programmable firmware operation with Static or Dynamic (Learning) switching tables
  • Full duplex Ethernet interfaces

Silicon Agnostic

  • Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Highly Configurable

  • Up to 36 ports configurable at compile time
  • Configurable queuing behavior (round-robin, fair queuing, etc.)
  • Supports Ethernet Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames

Easy to use

  • GMII interfaces for attaching to an external Physical Layer device (PHY)
  • Very easy integration with standard Xilinx AXI4 Lite control interface
  • Can be used in managed or unmanaged implementations

Deliverables

The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you

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Proven Quality

Solid process and predictability

Strong verification

agsdi-time

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research

Know-How

Long-term experience in communication protocols

Expert in executing digital design projects

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