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IEEE 1588 v2.1 PTP Solution

Timestamping Unit IP & Software Stack

Overview

Comcores IEEE 1588 Precision Time Protocol (PTP) Solution is a high quality and high performance time synchronization solution, including Timestamping Unit IP (TSU) and PTP Software Stack. The PTP solution is fully compliant with IEEE 1588 v2.1 and IEEE 1588 v2 standards and enables time synchronization across multiple devices. The solution supports IEEE 802.1AS profile making it ideal for TSN applications. Comcores timing solution supports IEEE 1588 PTP profiles such as IEEE Default and Peer-to-Peer, as well as ITU-T G.8275.1 and ITU-T G.8275.2 profiles.

The fully autonomously operated IP includes XGMII and GMII interfaces. User configuration allows easy configuration for various synchronization methods.

The PTP solution has been tested successfully on Xilinx ZCU102 development board as well as at system level thus enabling a fast-track solution for getting started with high performance time synchronization.

Time synchronization is crucial in many applications and industries, such as Wireless, Aerospace, Automotive, Industrial, and many others. Phase alignment method allows sub-nanosecond precision and enables even the most demanding applications, for example, 5G networks (Delivering timing accuracy in 5G networks whitepaper).

Block Diagram

Comcores 1588 Solution diagram

Key Features

Delivers Performance

  • High synchronization accuracy down to 3 ns
  • Supports Slave, Master, Ordinary Clock, Boundary Clock and Transparent Clock
  • Best Master Clock (BMC) selection algorithm
  • Support for PTP on Layer 2 (Ethernet) and Layer 3 (IPv4) interfaces
  • Up to 240 PTP domains supported
  • Supports PTP profiles defined in the standard
    • 1588 Default Profile
    • 1588 Peer-to-Peer Profile
    • IEEE 802.1AS
    • ITU-T G-8275.1
    • ITU-T G8275.2

      Highly Configurable

      • Configurable for many operating modes
      • Automatically calculates point-to-point latency
      • Has programmable eMAC and PHY ingress and egress latency
      • Supports GMII/XGMII interfaces

      Easy to use

      • Easy integration with MAC/PCS solutions
      • Pre-integrated with Altera or Xilinx Ethernet MAC cores; services available for integrating with other 3rd party eMAC cores
      • Complete reference designs for Altera and Xilinx, incl sample application software
      • Platform independent software

      Silicon Agnostic

      • Designed in VHDL and targeting targeting both ASICs and FPGAs

      Deliverables

      The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

      • Solid documentation, including User Manual and Release Note.
      • Programming Register Specification (optional).
      • Timing Constraints in Synopsys SDC format.
      • Access to support system and direct support from Comcores Engineers.
      • Software Application (optional).
      • Synopsys Lint and CDC (optional).
      • Synopsys SGDC Files (optional).
      • Synopsys Lint, CDC and Waivers (optional).

      Related Products

      Profiles Supported by the PTP IP

      Profile Name

      Default Delay Request-Response

      Default Peer-to-Peer

      Precision time protocol telecom profile for phase/time synchronization with full timing support from the network

      Precision time protocol telecom profile for time/phase synchronization with partial timing support from the network

      IEEE Std 802.1AS

      Defining Document

      IEEE Std 1588-2019 

      IEEE Std 1588-2019 

      G.8275.1

      G.8275.2

      IEEE Std 802.1AS-2020

      Application

      Generic

      Generic

      Telecommunication

      Telecommunication

      Audio/Video, Industrial Automation, Automotive

      Standards Development Organization

      IEEE

      IEEE

      ITU-T

      ITU-T

      IEEE

      What Comcores IP will do for you

      Proven Quality

      Solid process and predictability

      Strong verification

      Faster Time-to-Market

      First in bringing out new solutions

      Tremendous investments in research

      Know-How

      Long-term experience in communication protocols

      Expert in executing digital design projects

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      Morten Kofoed Esbjørn - Jan 20, 2023. The OCTAPUS initiative is an EU funded project, which started in September 2022 and is funded until February 2026. OCTAPUS stands for “Optical Circuit switched Time-Sensitive Network (TSN) architecture for highspeed Passive optical networks and next generation Ultra-dynamic & reconfigurable central office environments”, and the goal is to deliver an agile, low-cost and energy efficient Photonic Integrated Circuit (PIC) technology framework. OCTAPUS was...

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