The Interlaken controller IP is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting any ASIC or FPGA technologies.

The IP supports up to 2.6Tbps high-bandwidth performance and comes with an integrated Media Access layer. The IP has an extensive feature-set available and allows scalability in both number of lanes and lane speed. The IP-core is heavily tested in System Verilog random regression environment.

Block Diagram

Block Diagram of Comcores JESD204B IP

Key Features

Richly Featured

  • MAC layer with fast AMBA CXS interface
  • PCS layer highly configurable
  • 64B/67B encoding/decoding supported

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up


  • System Verilog random regression tested
    Lint/CDC checked

Silicon Agnostic

  • Targeting any RTL implementation like ASICs, and FPGAs


The IP core comes deeply verified, interoperability tested and with extensive documentation that, among others, includes User Manual and Release note. The product comes with a Basic RTL Test Bench, Constraint Files, and Test Reports. The core will by default come in an encrypted format. Source code option is available.

Please Contact us to discuss your project requirements.

What Comcores IP will do for you

Proven Quality

Solid process and predictability

Strong verification

Faster Time-to-Market

First in bringing out new solutions

Tremendous investments in research


Long-term experience in communication protocols

Expert in executing digital design projects

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