MACsec
100G / 200G / 400G / 800G / 1.6T
Ethernet Layer 2 Security solution for High speed applications
Overview
Comcores MACsec IP provides Ethernet Layer 2 Security for port authentication, data confidentiality and data integrity as standardized in IEEE 802.1AE. It protects components in Ethernet networks especially very high-speed Ethernet used in cloud, data center, and backhaul networks. The MACsec IP is a fully compliant solution that provides line-rate encryption and supports VLAN-in-Clear.
The core is configurable to have multiple Security Entities, SecYs, in a single IP to support multiple Connectivity Associations per port for traffic differentiation, and is prepared for easy interfacing with Comcores or third-party MAC, PCS and TSN Switch IPs. It implements a 128-bit MACsec data processing, where multiple 128-bit pipelines can be configured according to the target speed and input/output data interfaces. The IP can be configured for its placement above or below the MAC. It additionally includes a software tool for MACsec Key Agreement Protocol IEEE 802.1X integration.
Block Diagram
Technical Specifications
Key Features & Benefits
Delivers Performance
- Compliance with IEEE Std 802.1AE-2018
- Line-rate traffic encryption and decryption
Highly Configurable
- Supports 100G / 200G / 400G / 800G / 1.6T data rates
- Multiple Connectivity Associations (SecYs) with Traffic Mapping Rules
- Multiple integration contexts for placement above or below the MAC
Feature Rich
- AES-GCM-128 and AES-GCM-256 Cipher Suites with eXtended Packet Number (XPN)
- VLAN-in-Clear
- Confidentiality Offset
- Software tool for MACsec Key Agreement Protocol IEEE 802.1X integration
Silicon Agnostic
- Designed in Verilog and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note
- Simulation Environment, including Simple Testbed, Test case and Test Script
- Programming Register Specification
- Timing Constraints in Synopsys SDC format
- Access to support system and direct support from Comcores Engineers
- Synopsys SGDC Files (optional)
- Synopsys Lint, CDC and Waivers (optional)
