SGMII
Serial Gigabit Media Independent Interface
Overview
SGMII (Serial Gigabit Media Independent Interface) IP is a high-speed serial interface developed to connect a Gigabit Ethernet MAC (Media Access Controller) to a PHY (Physical Layer Device). It reduces the number of physical connections needed between Ethernet MACs and PHYs contributing to lowering power and cost.
The IP is ultra compact and is targeting ASIC’s and FPGA’s.
Block Diagram
Technical Specifications
Key Features & Benefits
Delivering Performance
- High-Speed Serial Interface
- Easy Integration with MACs and PHYs
- Compact Design for High Port Density applications
- Fully UVM verified
- Targeting ASIC’s and FPGA’s and has been taped out
Applications
- Ethernet PHY chips (e.g., Broadcom, Marvell, TI)
- Ethernet switch and SoC interfaces
- Automotive Ethernet modules
- FPGA-based Ethernet MAC/PHY implementations
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- IP in Source code or encrypted RTL
- Comprehensive documentation, including User Manual, Release Note and Product Brief
- Simulation Environment, including basic test environment, test cases and test scripts
- Access to a support system and direct support from Comcores Engineers