Morten Kofoed Esbjørn – Oct 31, 2022. 

Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The Interlaken protocol provides mechanisms to ensure the integrity of data transfer as well as manage data flows to ensure that the chip is not overloaded. These mechanisms effectively increase the operational reach of Interlaken interfaces as well as allow longer chip-to-chip connections.

Interlaken was introduced in 2006 as a high-speed chip-to-chip interface and a reliable packet transfer mechanism. It was inspired by XAUI and SPI4.2, and combined the best of both into one protocol. It combines the serial, channelized interface from XAUI with the flow control capabilities of SPI4.2.

Benefits of Interlaken

Interlaken provides efficiency

The challenge when connecting chips is to find an economic means of transferring data between the chip and the Print Circuit Board (PCB). This means using as few pins and PCB physical connections as possible. Serial interfaces are preferred as they drastically reduce the number of pins required. Secondly, serial interfaces consume less power and are less sensitive to electromagnetic interference compared to parallel connections.

Interlaken provides scalability

Interlaken employs SerDes technology to reduce the number of I/O pins, and as a serial interface it can still achieve long reach. This means Interlaken can be used in a variety of applications. Ideally each application will have a chip-to-chip interface that is optimized. However, in today’s climate it is far more desirable to have an interface that can be configured and reused to meet different requirements. For example, a chip-to-chip interface could be based on a single lane at full data capacity or alternatively, it could be based on 4 lanes each operating at a quarter of the data capacity.

Interlaken provides reliability

Interlaken is designed to be completely transparent, thus providing different reliability mechanisms to ensure correct data transmission.
First, Interlaken uses a more advanced block coding scheme to reduce running disparity as much as possible. A 64b/67b block scheme is used, where the 8-byte words to be transmitted are mapped or “striped” on a sequential basis to a 67-bit block. Using a larger block for encoding is more efficient and uses less bandwidth.

Second, CRC checks are applied at multiple levels, CRC32 at per-lane level and CRC24 at the data packet level, of Interlaken to ensure maximum data integrity. However, CRC checks can only indicate errors and not correct them. In 2020 the Interlaken Alliance published the Interlaken Reed-Solomon Forward Error Correction Extension Rev. 1.1, which defines how the RS(544, 514) FEC can be used in Interlaken to provide additional data integrity protection.

Third, a major advantage of the Interlaken interface is flow control. Interlaken implements a per-channel control mechanism, which enables the receiver to communicate backpressure. The flow status of each channel is communicated using a single bit indicating either a ‘1’ for ‘XON’ state or a ‘0’ for ‘XOFF’ state per logical channel. Data can be transmitted on a channel as long as the flow control status is XON.

Interlaken applications

Interlaken can be used in multiple applications, such as system-level, board-level and chip-level applications. Because of its configurability and scalability, it can be adapted to meet specific needs while ensuring a narrow, economic and reliable interface.

For smaller systems, that can be a single pizza-box motherboard where MAC/PHY chips are connected directly to the data processing unit (e.g., CPU, NPU, GPU or similar) or a switch/mapper chip. In these applications, Interlaken can be used to connect the MAC/PHY chips to the data processing unit or switch. Interlaken flow control and rate matching can be used in switch systems to manage the flow of input/output data based on the FIFO buffers for each switch port ensuring that no packet data is dropped in the system.

As board-level design is limited due to the size of the board, compact designs are important. Interlaken provides advantages such as reducing the cost, power consumption and complexity of the board design, because only a minimum required physical lanes need to be implemented. Since board designs can involve multiple chips in the data path, Interlaken can be used to meet the individual requirements of each chip interface with respect to number of lanes and speed rates. Flow control and rate matching again can be used here to match data rates in applications where there can be clock or data rate discrepancies between chips.

Large System- and board-level example applications

According to a recent report from PwC, global data consumption in 2020 increased by 30.4% compared to 2019 and is expected to grow by 26.9% per year until 2025. This requires higher speeds and capacities, which means bigger chips and greater power consumption. Power consumption is a major challenge for data centers and is as important as speed and capacity in decisions on which networking technology and chips to deploy. Space is also an issue, so compact solutions are important. The challenge, for both system and chip designers, is to minimize the cost, size and power consumption of systems and chips as much as possible.

This is leading chip designers to break up designs so that they can either be implemented on multiple physical chips or on ‘chiplets’, which are smaller chip dies that are combined with high-speed interfaces to form an efficient solution within a single package. This technique has been used by CPU manufacturers for some time and can also be seen in “System-on-Chip” (SoC) solutions.

Another chip-level application of Interlaken is System-on-Chip (SoC) solutions where FPGA logic is combined with hard-coded blocks or separate dies in the same package. A good example of this is SoC solutions supporting digital or even analog signal processing. The signal processing functionality can be provided on a separate die that is optimized for this kind of functionality. Interlaken provides an efficient and reliable interface for connecting blocks and separate dies with the FPGA logic.

To get a more in-depth look at Interlaken, read our whitepaper, watch our webinar or click here for questions about our Interlaken IP.