Overview

The 10M/100M/1G/2.5G Ethernet TSN End Station Controller IP from Comcores is a comprehensive hardware and software solution for automotive, aerospace and industrial applications.  The solution implements Timing & Synchronization (802.1AS), Multiple types of Traffic Shaping (802.1Qav, 802.1Qby, 802.1Qcr), Frame preemption (802.1Qbu), Frame replication & elimination (802.1CB), Steam filtering & policing (802.1Qci), and optional MACsec encryption/decryption (802.1AE).

The solution is designed to provide high-precision time synchronization and accurate traffic scheduling. It supports up to 8 traffic classes, each with a dedicated queue for all ports. 

The 10M/100M/1G/2.5G Ethernet TSN End Station Controller IP version is envisioned for demanding applications that demand high bandwidth, reliable and secure real-time communication and precision time synchronization.

 The IP supports 10M/100M/1G/2.5G operation and utilizes standard GMII/RGMII/SGMII and MDIO interfaces to communicate with Ethernet Physical layer devices. Its configuration and status register are accessible via a 32-bit AXI4-lite bus and include a multichannel high-performance DMA controller to transfer packets between the network interface and a host processor system. The DMA controller is connected to the host processor system via a memory-mapped AXI4 master port.

The 10M/100M/1G/2.5G Ethernet TSN End Station controller IP includes a comprehensive software package with device drivers for several operating systems, a software stack for 802.1AS and a complete demonstration system based on Linux. The solution is available as technology-independent RTL source code (System Verilog) or encrypted netlist for ASIC and FPGA implementation. Furthermore, FPGA based hardware platforms are available for evaluation and prototyping.

Block Diagram

Technical Specifications

Key Features & Benefits

Versatile Solution

•  Fully integrated hardware and software solution
•  One physical Ethernet port and dedicated host port
• Seamless integration with host CPU or external micro-controller 
• DMA engine with dedicated channels for RX/TX with AXI-MM interface
• GMII/RGMII/SGMII Ethernet physical layer transceiver support

Robust Design

• Time synchronization as per IEEE 802.1AS with grandmaster and slave support
• Traffic scheduling as per IEEE 802.1Qav and IEEE 802.1Qbv
• Frame preemption as per IEEE 802.1Qbu
• Supports up to 8 traffic classes per port
• Stream filtering & policing as per IEEE 802.1Qci

Optional Features

•  MACsec encryption/decryption as per IEEE 802.1AE
•  Asynchronous traffic scheduling as per IEEE 802.1Qcr
•  Frame replication & elimination as per IEEE 802.1CB

Silicon Agnostic

• Designed in Verilog and targeting both ASICs and FPGAs

Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

• Solid documentation, including User Manual and Release Note
• Simulation Environment, including Simple Testbed, Test case and Test Script
• Programming Register Specification
• Timing Constraints in Synopsys SDC format
• Access to support system and direct support from Comcores Engineers
• Synopsys SGDC Files (optional)
• Synopsys Lint, CDC and Waivers (optional)

Omni500 – Configurable evaluation and prototyping platform