May 2, 2023.

The JESD204 Standard which was first introduced in 2006 is one of the key standardized serial interface between data converters (ADCs and DACs) and logic devices (FPGAs or ASICs) and has come a long way since its introduction, evolving with multiple iterations from JESD204B to JESD204C.

The latest iteration of this standard the JESD204D is expected to release in Q4 2023 and if you are curious about the latest developments expected in the JESD204 standard, then keep reading on as we make our prediction about what we expect the upcoming JESD204D will contain based on our expertise with JESD204 and being a member of the JEDEC TG16-4 Task Group standardization committee for JESD204D.

What to expect from JESD204D

JESD204D will continue to use NRZ signaling, like the previous versions of the standard, with the addition of PAM4 signaling as a new feature. Each will be running up to 58 Gbaud, which means 116 Gbps in PAM4 and 58 Gbps in NRZ (PAM2). PAM4, which seems to be the natural progression to achieve higher line rates, requires RS-FEC encoding due to its high BER (Bit Error Rate).

Accordingly, the big new feature for the JESD204D protocol will be the Reed Solomon Forward Error Correction (RS FEC) encoding. This is required due to the high Bit Error Rate (BER) on PAM 4 links, meaning that RS FEC is used for error detection and correction. NRZ or PAM2 links will still use part of the FEC mechanism, but only for error detection in place of the CRC mechanism.

The framing will be oriented around FEC Code words, and instead of Sync Header bits (of the 64b66b encoding in JESD204C) we will now have Sync Header Burster, which will be used for boundary detection of FEC Code Words.

There is no change in the transport layer and multiple converter devices aligned across multiple lane links is still being supported.

RS FEC encoding with Sync Header Burst

JESD204D RS FEC Symbol Oriented Framing

There are new Link Layer configuration parameters for RS FEC Encoding, and thus a few new letters are introduced.

  • P, Number of payload bytes (octets) in one FEC code word.
    • This can be 160, 320 or 640 Bytes. Assuming a single payload block is 160 Bytes, we can say the FEC code word will carry 1, 2 or 4 payload blocks
  • n, Number of 10-bit symbols in one FEC code word.
    • 160 Bytes (or 1280 bits) will be represented as 128 10-bit symbols for FEC processing
  • k, Number of 10-bit message symbols in one FEC Code word
    • RS FEC encoding also encodes the additional 2 symbols that are prepended to the payload as the Sync Header Burst. A 128-symbol payload becomes 130 symbol message for encoding.
  • t, Number of 10-bit symbol errors that can be corrected
  • A, Number of payload blocks in one alignment block
    • Used for organizing Larger Framing structure. It is the equivalent of E (in JESD204C) or K (in JESD204B
JESD204D RS FEC Symbol Oriented Framing
RS FEC table

Subclass 0, 1 and 3

The standard will contain Subclass 0, Subclass 1 with deterministic latency, and Subclass 3. The new Subclass 3 MULTIREF mechanism already existed in the JESD204C specification but did not have its own subclass designation. Thus, Subclass 3 will receive its own designation in JESD204D, and is defined for systems using MULTIREF instead of SYSREF for multipoint links. It does not offer deterministic latency however, it can be used when you do not have SYSREF but wish to align multiple devices on the TX or RX side with each other, allowing them to have a common local reference used for aligning lanes on a common Local Alignment Clock (LAC) boundary.

In Subclass 0, there is no deterministic Latency, and no way to align lanes coming to or from multiple converters. Data will be released from the de-skewed buffer as soon as it arrives on all the lanes.

In Subclass 1, there is deterministic Latency with the use of SYSREF for Alignment. Data is released from the de-skewed buffer at fixed offsets from the LAC in relation to Global System Reference (SYSREF).

Subclass 2 exists in JESD204B and made use of the Sync signal, which no longer exists in self synchronizing receivers of JESD204C and JESD204D. Hence why it is skipped in JESD204D to avoid any confusion.

A quick comparison of JESD204A, JESD204B, JESD204C and JESD204D

JESD204 standard has been continuously evolving since introduction to meet application and speed needs, many features and different data encoding have been added throughout the different standard iterations, illustrated in the table below.

JESD history from JESD204-JESD204D

We will continue to keep you updated on the latest with JESD204D. For more information you can watch our JESD204D prediction webinar or contact us here.