Pipelined FFT
Overview
Comcores Fast Fourier Transform (FFT) IP core is an implementation of a Cooley-Tukey FFT algorithm, a computationally efficient method for calculating the Discrete Fourier Transform (DFT). The FFT IP uses a Radix-2, Decimation-In-Time (DIT) and pipelined architecture targeting high performance systems where high throughput is a key requirement.
The FFT IP core comes with a large variety of run-time configurations such as FFT/IFFT mode, gain control, and transform size which makes it suitable for a large variety of applications such as OFDM systems (e.g. LTE or New Radio) and real-time signal analysis. For any high performance application the FFT IP core delivers on your need for speed and performance whether the target is FPGA or ASIC.
Block Diagram
Key Features
Richly Featured
- Supports both FFT and IFFT transformation
- Uses a Cooley-Tukey decimation in time algorithm with radix-2 sizes and pipelined architecture
- Scaled fixed-point, where user provides the scaling schedule or block floating-point with run-time automatic adjusted scaling
- Complex input and output
- Accepts input sample every clock cycle
- Automatic or manual gain control
Silicon Agnostic
- Designed in SystemVerilog and targeting both ASICs and FPGAs
Highly Configurable
- Configurable for many operating modes
- Support both FFT and IFFT computations
- Run-time configurable transform lengths of size 8 – 65535
- Natural or bit-reversed ordering on inputs
- Direct or natural ordering on output
- Single RTL code base supports all configurations
Easy to use
- Simple configuration signals for run-time configurations
and enabling/disabling of features - Test bench is included
- Comes with a bit-accurate software model for easy performance evaluation in evaluation tools e.g. Matlab
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Product Brief.
- Simulation Environment, including Simple Testbed, Test case and Test Script.
- Software Model included.
- Access to support system and direct support from Comcores Engineers.
- Timing Constraints in Synopsys SDC format (optional).
- Synopsys Lint (optional).
- Synopsys Lint waiver (optional).
Related Products
What Comcores IP will do for you
Proven Quality
Solid process and predictability
Strong verification
Faster Time-to-Market
First in bringing out new solutions
Tremendous investments in research
Know-How
Long-term experience in communication protocols
Expert in executing digital design projects
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